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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TLK6002 датащи(PDF) 12 Page - Texas Instruments |
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TLK6002 датащи(HTML) 12 Page - Texas Instruments |
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12 / 98 page  TLK6002 SLLSE34A – MAY 2010 – REVISED AUGUST 2010 www.ti.com Table 2-1. Pin Description – Signal Pins (continued) Terminal Direction Type Description Signal BGA Supply Port Address. Used to select the Port ID. PRTAD[4:1] selects the device port address. TLK6002 has two different PHY addresses (ports). Selecting a unique PRTAD[4:1] per TLK6002 device allows 16 TLK6002 devices per MDIO bus. Each channel can be accessed by setting the appropriate port address field within the serial interface protocol transaction. TLK6002 will respond if the 4 MSB’s of the inband PHY address field on MDIO protocol (PA[4:1]) matches Input PRTAD[4:1]. The LSB of PHY address field (PA[0]) will determine which channel/port within TLK6002 to respond to. LVCMOS V15 1.5V/1.8V PRTAD[0] is not used functionally, but is present for device testability and compatibility with other devices in the M8 VDDO2/ family of products. PRTAD[4:0] K12 VDDO1/ K11 Channel A responds to port address 0 within the block of two port addresses. VDDO1/ L11 VDDO1/ Channel B responds to port address 1 within the block of two port addresses. VDDO1 PRTAD[0] should be grounded on the application board. The PRTAD[3] pin in application mode should be biased with a pull up or pull down resistor (or allow for an isolation mechanism from the on board driver), and not connected directly to a power or ground plane. The application board should allow the flexibility of easily reworking the PRTAD[3] signal to a high level if device debug is necessary (by including an uninstalled resistor to VDDO1). Input Low True Device Reset. When asserted (low logic level), this signal resets the entire TLK6002 device. RESET_N LVCMOS must be held asserted for at least 10 µS after device power stabilization. RESET_N V1 1.5V/1.8V VDDO3 Input MDIO clock input. Clock input for the Clause 22 MDIO interface. LVCMOS Note that an external pullup is generally not required on MDC. MDC T1 w/Hysteresi s 1.5V/1.8V VDDO3 MDIO data I/O. MDIO interface data input/output signal for the Clause 22 MDIO interface. Input/ This signal must be externally pulled up to VDDO3, using a 2 k Ω resistor. Output During device reset (RESET_N asserted low) this pin is floating. During software initiated power down the LVCMOS MDIO U2 management interface remains active for control register writes and reads. Certain status bits are not deterministic 1.5V/1.8V as their generating clock source may be disabled as a result of asserting either power down input signal. During pin VDDO3 25 Ω based power down (PD_TRXA_N and PD_TRXB_N asserted low), this pin is floating. During register based power Driver down (1.15 asserted high both channels), this pin is driven normally. SPI Clock (SPI_CLK). Defaults to Output, Driven Low. Can be used as a SPI interface or a generic customer controllable I/O interface. When used as part of the SPI interface, this signal is the SPI clock to be used with Input/ external TI Jitter cleaner or clock Distribution device. Output Three register bits (15.14:12) control this I/O signal. See the detailed register bit description for operational detail. LVCMOS SCL H13 If unused in the application, this signal can be left floating. 1.5V/1.8V Careful programming is required to prevent accidental contention with simultaneous external drivers. During device VDDO1 25 Ω reset (RESET_N asserted low) this pin is driven low. During pin based power down (PD_TRXA_N and PD_TRXB_N Driver asserted low), this pin is floating. During register based power down (1.15 asserted high both channels), these pins are driven per register setting SPI Data. Defaults to Input. Can be used as a SPI interface or a generic customer controllable I/O interface. When used as part of the SPI interface, this signal is the SPI data from the external TI Jitter cleaner or clock Distribution Input/ device to the TLK6002. Output Three register bits (15.10:8) control this I/O signal. See the detailed register bit description for operational detail. LVCMOS SDO K13 If unused in the application, this signal should be pulled to ground. Careful programming is required to prevent 1.5V/1.8V accidental contention with simultaneous external drivers. VDDO1 25 Ω During device reset (RESET_N asserted low) this pin is floating. During pin based power down (PD_TRXA_N and Driver PD_TRXB_N asserted low), this pin is floating. During register based power down (1.15 asserted high both channels), these pins are driven per register setting. SPI Data. Defaults to Output, driven low. Can be used as a SPI interface or a generic customer controllable I/O interface. When used as part of the SPI interface, this signal is the SPI data from TLK6002 to the external TI Jitter Input/ cleaner or clock Distribution device. Output Three register bits (15.6:4) control this I/O signal. See the detailed register bit description for operational detail. LVCMOS SDI E14 If unused in the application, this signal can be left floating. 1.5V/1.8V Careful programming is required to prevent accidental contention with simultaneous external drivers. During device VDDO1 25 Ω reset (RESET_N asserted low) this pin is driven low. Driver During pin based power down (PD_TRXA_N and PD_TRXB_N asserted low), this pin is floating. During register based power down (1.15 asserted high both channels), these pins are driven per register setting. SPI Chip Select. Defaults to Output, Driven High. Can be used as a SPI interface or a generic customer controllable I/O interface. When used as part of the SPI interface, this signal is the chip select for the external TI Input/ Jitter cleaner or clock Distribution device. Low=Select Device. High=Device Not Selected. Output Three register bits (15.2:0) control this I/O signal. See the detailed register bit description for operational detail. LVCMOS CS_N D14 If unused in the application, this signal can be left floating. Careful programming is required to prevent accidental 1.5V/1.8V contention with simultaneous external drivers. VDDO1 25 Ω During device reset (RESET_N asserted low) this pin is driven high. During pin based power down (PD_TRXA_N Driver and PD_TRXB_N asserted low), this pin is floating. During register based power down (1.15 asserted high both channels), these pins are driven per register setting. 12 Description Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK6002 |
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