the effect of redistributing the charge stored in the capaci-

tance of the panel columns. Since half the columns are at

voltages more positive than V

tive, this redistribution of charge or “charge-sharing” has the

effect of pulling all of the columns to a neutral voltage near

the middle of the driver’s dynamic range. Thus, the voltages

on all the columns are driven approximately halfway toward

their next value with no power expended. This dramatically

reduces panel power dissipation (up to a theoretical limit of

50%) compared to conventional drivers which must drive

each column through the entire voltage swing every time

polarity is reversed.

PIN DESCRIPTIONS

The pin order configuration for the FPD03784 is shown in fig.

3. Optional pins do not need to be carried off a custom TCP

or COP package but may require a connection to a neigh-

boring pad on the die by a tie on the tape. The following

paragraphs describe the function of the FPD03784 pins.

CSTIME —

CHARGE SHARE TIME (INPUT)

The input controls how long the outputs are in charge share

mode following each LOAD signal. The CSTIME input from

all of the column drivers should be tied together and con-

nected to VSS1 through a parallel combination of RC. The

charge time is determined by the equation:

T

A typical capacitance of 100pF should be chosen to swamp

parasitic board and I/O pin effects. See

Figure 1.

CLK —

DATA CLOCK (INPUT)

Clock input for data on Dx[0:5].

DX[5:0] —

DATA BUS (INPUT)

DA[5:0] — Data Input Pins for OUTPUTS 1, 7...379

DB[5:0] — Data Input Pins for OUTPUTS 2, 8...380

DC[5:0] — Data Input Pins for OUTPUTS 3, 9...381

DD[5:0] — Data Input Pins for OUTPUTS 4, 10...382

DE[5:0] — Data Input Pins for OUTPUTS 5, 11...383

DF[5:0] — Data Input Pins for OUTPUTS 6, 12...384

ENIO1/ENIO2 —

DATA LOADING ENABLE 1 AND 2 (I/O)

If UP = H, then the ENIO1 pin is configured as an input and

the ENIO2 pin is configured as an output. If UP = L, then the

ENIO2 pin is configured as an input and the ENIO1 pin is

configured as an output.

INVTABC —

DIGITAL DATA INVERT (INPUT)

When INVERT = L, input data from DA[0:5], DB[0:5] and

DC[0:5] is inverted. The INVTABC pin can be tied to

INVTDEF on the TCP to form a single INVERT pin, or

operated independently from each other.

INVTDEF —

DIGITAL DATA INVERT (INPUT)

When INVERT = H, input data from DD[0:5], DE[0:5] and

DF[0:5] is inverted. The INVTABC pin can be tied to

INVTDEF on the TCP to form a single INVERT pin, or

operated independently from each other.

I

CURRENT FOR OUTPUT DRIVE

(INPUT)

The I

output drive current (I

column line, RC network load. Current flow out of the I

REF

pin is used to set the rise and fall slew rate of the output

waveform. This current is supplied through an external re-

sistor (R

tied between the I

REF

pin (held by the

FPD03784 at V

separate R

I

The I

mance of the FPD03784 output-stage amplifiers. Increasing

I

time but also increases power consumption. Normally, I

set to 40µA, which provides a good balance between power

consumption and amplifier bandwidth. The flexibility to adjust

I

applications where low power is of extreme interest (I

40µA).

The I

(R

be computed as follows:

One resistor (R

resistor is connected to the I

the current going into this pin is copied to the I

pin for cascading to the next driver. See

Figure 1. Note that

I

I

This output pin supplies the I

of the next driver in the row (see

Figure 1). The I

the last driver should be left floating. Optionally, this pin can

be left floating on each driver if the designer wishes to

provide a separate I

adds resistor component count, it reduces input lead count.

LOAD —

DATA LOAD (INPUT)

The falling edge of LOAD copies the digital video buffered by

the shift register into a second latch beginning the D to A

conversion. Immediately following the fall of LOAD, the out-

puts are forced into charge share mode for the time set by

the CSTIME input. The outputs then drive the D to A con-

verted voltages following the CSTIME.

POL —

POLARITY (INPUT)

When POL = L, odd numbered outputs (1, 3, 5, ...383) are

controlled by VGMA7 through VGMA12 and even numbered

outputs are controlled by VGMA1 through VGMA6. When

POL = H, odd numbered outputs are controlled by VGMA1

through VGMA6 and even numbered outputs are controlled

by VGMA7 through VGMA12.

SINGLE —

SINGLE/DUAL-EDGE CLOCK ENABLE (IN-

PUT)

This pin controls single/dual-edge clocking. When SINGLE is

high, single-edge clocking is enabled, and input data is

latched only on the falling edge of CLK. When SINGLE is

low, dual-edge clocking is enabled, and input data is latched

on both the rising and falling edges of CLK.

Optional — The SINGLE die pad is bounded on each side

by a logic High and a logic Low pad. This allows the state of

SINGLE to be chosen on the TCP to eliminate an input pin.

UP —

DATA SHIFT DIRECTION — UP OR DOWN (INPUT)

The UP pin controls the data shift direction. If UP is high then

data is shifted “up” from output 1 to output 384, ENIO1 is

configured as an input, and ENIO2 is an output. If UP is low

then data is shifted “down” from output 384 to output 1,

ENIO2 is an input, and ENIO1 is an output.

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