LM49200, LM49200TLEVAL

SNAS459A – MAY 2009 – REVISED APRIL 2013

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HPR_SD BIT

The HPR_SD bit will deactivate the right headphone output amplifier. This bit is provided to reduce power

consumption when only one headphone output is needed.

MODE_CONTROL BITS

In the LM49200 OUTPUT MODE CONTROL register (Table 4), Bit B5 (EP Bypass) controls the operation of the

Earpiece Bypass path. If EP Bypass = 0, it would act under normal output mode operation set by bits B3, B2, B1,

and B0. If EP Bypass = 1, it overrides the B3, B2, B1, and B0 Bits and enables the Receiver Bypass path, a

class AB amplifier, to the speaker output.

Bit B4 (HPR_SD) of the OUPUT MODE CONTROL register controls the right headphone shutdown. If HPR_SD

= 1, the right headphone output is disabled.

The LM49200 includes a comprehensive mixer multiplexer controlled through the I2C interface. The

mixer/multiplexer allows any input combination to appear on any output of LM49200. Multiple input paths can be

selected simultaneously. Under these conditions, the selected inputs are mixed together and output on the

selected channel. Table 5 shows how the input signals are mixed together for each possible input selection.

HP_GAIN BITS

The headphone outputs have an additional, single volume control set by the three HP_Gain bits in the Output

Gain Control register. The HP_Gain volume setting controls the output level for both the left and the right

headphone outputs.

LS (EP_MODE) BIT

The LS (EP_Mode) bit selects the amount of bias current in the loudspeaker amplifier. Setting the LS (EP_Mode)

bit to a '1' will reduce the amount of current from the VDDLS supply by approximately 0.5mA. The THD

performance of the loudspeaker amplifier will be reduced as a result of lower bias current. See the performance

graphs in Typical Performance Characteristics above.

VOLUME CONTROL BITS

The LM49200 has three independent 32-step volume controls, one for each of the inputs. The five bits of the

Volume Control registers sets the volume for the specified input channel.

SHUTDOWN FUNCTION

The LM49200 features the following shutdown controls.

Bit B4 (GAMP_SD) of the SHUTDOWN CONTROL register controls the gain amplifiers. When GAMP_SD = 1, it

disables the gain amplifiers that are not in use. For example, in Modes 1, 4 and 5, the Mono inputs are in use, so

the Left and Right input gain amplifiers are disabled, causing the IDD to be minimized.

Bit B0 (PWR_On) of the SHUTDOWN CONTROL register is the global shutdown control for the entire device.

Set PWR_On = 0 for normal operation. PWR_On = 1 overrides any other shutdown control bit.

DIFFERENTIAL AMPLIFIER EXPLANATION

The LM49200 features a differential input stage, which offers improved noise rejection compared to a single-

ended input amplifier. Because a differential input amplifier amplifies the difference between the two input

signals, any component common to both signals is cancelled. An additional benefit of the differential input

structure is the possible elimination of the DC input blocking capacitors. Since the DC component is common to

both inputs, and thus cancelled by the amplifier, the LM49200 can be used without input coupling capacitors

when configured with a differential input signal.

BRIDGE CONFIGURATION EXPLAINED

By driving the load differentially through the MONO outputs, an amplifier configuration commonly referred to as

“bridged mode” is established. Bridged mode operation is different from the classical single-ended amplifier

configuration where one side of the load is connected to ground.

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