SDA

SCL

S

P

START condition

STO

P condition

LM49200, LM49200TLEVAL

SNAS459A – MAY 2009 – REVISED APRIL 2013

www.ti.com

APPLICATION INFORMATION

I

2C COMPATIBLE INTERFACE

The LM49200 is controlled through an I2C compatible serial interface that consists of a serial data line (SDA) and

a serial clock (SCL). The clock line is uni-directional. The data line is bi-directional (open drain). The LM49200

and the master can communicate at clock rates up to 400kHz. Figure 32 shows the I2C interface timing diagram.

Data on the SDA line must be stable during the HIGH period of SCL. The LM49200 is a transmit/receive slave-

only device, reliant upon the master to generate the SCL signal. Each transmission sequence is framed by a

START condition and a STOP condition (Figure 33). Each data word, device address and data, transmitted over

the bus is 8 bits long and is always followed by an acknowledge pulse (Figure 34). The LM49200 device address

is 11111000.

I

2C INTERFACE POWER SUPPLY PIN (I2CV

DD)

The LM49200's I2C interface is powered up through the I2CVDD pin. The LM49200's I

2C interface operates at a

voltage level set by the I2CVDD pin which can be set independent to that of the main power supply pin VDD. This

is ideal whenever logic levels for the I2C interface are dictated by a microcontroller or microprocessor that is

operating at a lower supply voltage than the main battery of a portable system

I

2C BUS FORMAT

The I2C bus format is shown in Figure 34. The START signal, the transition of SDA from HIGH to LOW while

SCL is HIGH, is generated, alerting all devices on the bus that a device address is being written to the bus.

The 7-bit device address is written to the bus, most significant bit (MSB) first, followed by the R/W bit. R/W = 0

indicates the master is writing to the slave device, R/W = 1 indicates the master wants to read data from the

slave device. Set R/W = 0; the LM49200 is a WRITE-ONLY device and will not respond to the R/W = 1. The data

is latched in on the rising edge of the clock. Each address bit must be stable while SCL is HIGH. After the last

address bit is transmitted, the master device releases SDA, during which time, an acknowledge clock pulse is

generated by the slave device. If the LM49200 receives the correct address, the device pulls the SDA line low,

generating an acknowledge bit (ACK).

Once the master device registers the ACK bit, the 8-bit register data word is sent. Each data bit should be stable

while SCL is HIGH. After the 8-bit register data word is sent, the LM49200 sends another ACK bit. Following the

acknowledgement of the register data word, the master issues a STOP bit, allowing SDA to go high while SCL is

high.

Figure 32. I2C Timing Diagram

Figure 33. Start and Stop Diagram

14

Submit Documentation Feedback

Copyright © 2009–2013, Texas Instruments Incorporated

Product Folder Links: LM49200 LM49200TLEVAL