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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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L5985 датащи(PDF) 19 Page - STMicroelectronics |
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L5985 датащи(HTML) 19 Page - STMicroelectronics |
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19 / 36 page  L5985 Application informations 19/36 5.4.1 Type III compensation network The methodology to stabilize the loop consists of placing two zeros to compensate the effect of the LC double pole, so increasing phase margin; then to place one pole in the origin to minimize the dc error on regulated output voltage; finally to place other poles far away the zero dB frequency. In Figure 10 the type III compensation network is shown. This network introduces two zeros (fZ1, fZ2) and three poles (fP0, fP1, fP2). They expression are: Equation 16 Equation 17 Figure 10. Type III compensation network In Figure 11 the Bode diagram of the PWM and LC filter transfer function (GPW0 · GLC(f)) and the open loop gain (GLOOP(f) = GPW0 · GLC(f) · GTYPEIII(f)) are drawn. f Z1 1 2 π C 3 R 1 R 3 + () ⋅⋅ ------------------------------------------------ = f Z2 1 2 π R 4 C 4 ⋅⋅ ------------------------------ = , f P0 0 = f P1 1 2 π R 3 C 3 ⋅⋅ ------------------------------ = f P2 1 2 π R 4 C 4 C 5 ⋅ C 4 C 5 + -------------------- ⋅⋅ -------------------------------------------- = ,, |
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