

2024 Microchip Technology Inc. and its subsidiaries.

DS20006843A-page 21

ZL40262

Output frequency

FMAX

—

—

400

MHz

—

Output-to-output skew

tOOSK

—

—

50

ps

—

Device-to-device output skew

tDOOSK

0.75

—

129

ps

—

Input-to-output delay

tOPD

—

0.85

1

ns

—

Output enable time

tEN

—

—

3

cycles

—

Output disable time

tDIS

—

—

3

cycles

—

Note 1: Values are over recommended operating conditions.

2: Measurement taken from single ended waveform.

3: Measurement taken from differential waveform.

4: Measured from -150 mV to +150 mV on the differential waveform (derived from CK minus CK#) The signal

must be monotonic through the measurement region for rise and fall time. The 300 mV measurement win-

dow is centered on the differential zero crossing. See Figure 3-4.

5: Measured at crossing point where the instantaneous voltage value of the rising edge of CK equals the fall-

ing edge of CK#. See Figure 3-1.

6: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is

crossing. Refers to all crossing points for this measurement. See Figure 3-1.

7: This requirement—from PCI Express Base Specification, Revision 4.0—is applicable only to clock genera-

tors and not to buffers. A clock buffer is a transparent device whose output clock period follows the input

clock period.

8: Defined as the maximum instantaneous voltage including overshoot. See Figure 3-1.

9: Defined as the minimum instantaneous voltage including undershoot. See Figure 3-1.

10: Defined as the total variation of all crossing voltages of Rising CK and Falling CK# This is the maximum

allowed variance in VCROSS for any particular system. See Figure 3-2.

11: The PPM requirement—from PCIe Express Base Specification, Revision 4.0—is related to clock genera-

tion devices. This requirement is not applicable to buffers because buffer’s output frequency accuracy is

identical to the frequency accuracy of the source driving the buffer.

12: The tSTABLE is the time the differential clock must maintain a minimum ±150 mV differential voltage after

20 rising/falling edges before it is allowed to droop back into the VRB ±100 mV differential range. See Fig-

ure 3-5.

13: Matching applies to rising edge rate for CKx and falling edge rate for CK#x. It is measured using a ±75 mV

window centered on the median cros point where CKx rising meets CK#x falling. The median cross point

is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The

Rise Edge Rate of CKx should be compared to the Fall Edge Rate of CK#x the maximum allowed differ-

ence should not exceed 20% of the slowest edge rate. See Figure 3-3.

14: Clock DC impedance tolerance depends only on the tolerance of external 50Ω shunt resistors used in

HCSL. The test used resistors with +/-1% tolerance.

TABLE 3-9:

HCSL OUTPUTS FOR VDDO = 2.5V (CONTINUED)

Note 1

Parameter

Symbol

Min

Typ.

Max

Units

Condition