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ADC14C080 датащи(PDF) 3 Page - Texas Instruments |
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ADC14C080 датащи(HTML) 3 Page - Texas Instruments |
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3 / 32 page ![]() AGND VA AGND VA AGND VA VA VA VA VA AGND AGND VA AGND ADC14C080 www.ti.com SNAS375C – SEPTEMBER 2006 – REVISED APRIL 2013 Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit Description ANALOG I/O 5 VIN+ Differential analog input pins. The differential full-scale input signal level is 2VP-P with each input pin signal centered on a common mode 6 VIN- voltage, VCM. 2 VRP 32 VCMO These pins should each be bypassed to AGND with a low ESL (equivalent series inductance) 0.1 µF capacitor placed very close to the pin to minimize stray inductance. A 0.1 µF capacitor should be placed between VRP and VRN as close to the pins as possible, and a 1 µF capacitor should be placed in parallel. VRP and VRN should not be loaded. VCMO may be loaded to 1mA for 1 VRN use as a temperature stable 1.5V reference. It is recommended to use VCMO to provide the common mode voltage, VCM, for the differential analog inputs, VIN+ and VIN−. Reference Voltage. This device provides an internally developed 1.2V reference. When using the internal reference, VREF should be decoupled to AGND with a 0.1 µF and a 1 µF low equivalent series 31 VREF inductance (ESL) capacitor . This pin may be driven with an external 1.2V reference voltage. This pin should not be used to source or sink current. This is a four-state pin controlling the input clock mode and output data format. OF/DCS = VA, output data format is 2's complement without duty cycle stabilization applied to the input clock OF/DCS = AGND, output data format is offset binary, without duty 12 OF/DCS cycle stabilization applied to the input clock. OF/DCS = (2/3)*VA, output data is 2's complement with duty cycle stabilization applied to the input clock OF/DCS = (1/3)*VA, output data is offset binary with duty cycle stabilization applied to the input clock. DIGITAL I/O The clock input pin. 11 CLK The analog input is sampled on the rising edge of the clock input. This is a two-state input controlling Power Down. 30 PD PD = VA, Power Down is enabled and power dissipation is reduced. PD = AGND, Normal operation. Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: ADC14C080 |
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