ADC12C080

SNAS379C – SEPTEMBER 2006 – REVISED APRIL 2013

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FUNCTIONAL DESCRIPTION

Operating on a single +3.0V supply, the ADC12C080 uses a pipeline architecture and has error correction

circuitry to help ensure maximum performance. The differential analog input signal is digitized to 12 bits. The

user has the choice of using an internal 1.2V stable reference, or using an external 1.2V reference. Any external

reference is buffered on-chip to ease the task of driving that pin.

The output word rate is the same as the clock frequency. The analog input is acquired at the rising edge of the

clock and the digital data for a given sample is delayed by the pipeline for 7 clock cycles. The digital outputs are

CMOS compatible signals that are clocked by a synchronous data ready output signal (DRDY, pin 21) at the

same rate as the clock input. Duty cycle stabilization and output data format are selectable using the quad state

function OF/DCS pin (pin 12). The output data can be set for offset binary or two's complement.

Power-down is selectable using the PD pin (pin 30). A logic high on the PD pin reduces the converter power

consumption. For normal operation, the PD pin should be connected to the analog ground (AGND).

APPLICATIONS INFORMATION

OPERATING CONDITIONS

We recommend that the following conditions be observed for operation of the ADC12C080:

2.7V

≤ VA ≤ 3.6V

2.4V

≤ VDR ≤ VA

20 MHz

≤ fCLK ≤ 80 MHz

1.2V internal reference

VREF = 1.2V (for an external reference)

VCM = 1.5V (from VCMO)

ANALOG INPUTS

Signal Inputs

Differential Analog Input Pins

The ADC12C080 has one pair of analog signal input pins, VIN+ and VIN−, which form a differential input pair. The

input signal, VIN, is defined as

VIN = (VIN+) – (VIN−)

(4)

Figure 30 shows the expected input signal range. Note that the common mode input voltage, VCM, should be

1.5V. Using VCMO (pin 32) for VCM will ensure the proper input common mode level for the analog input signal.

The positive peaks of the individual input signals should each never exceed 2.6V. Each analog input pin of the

differential pair should have a maximum peak-to-peak voltage of 1V, be 180° out of phase with each other and

be centered around VCM. The peak-to-peak voltage swing at each analog input pin should not exceed the 1V or

the output data will be clipped.

Figure 30. Expected Input Signal Range

For single frequency sine waves the full scale error in LSB can be described as approximately

20

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