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TMP461-SP

SBOS876B – SEPTEMBER 2017 – REVISED FEBRUARY 2020

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Programming (continued)

Table 4. TMP461-SP Slave Address Options

A1 CONNECTION

A0 CONNECTION

SLAVE ADDRESS

BINARY

HEX

GND

GND

1001 000

48

GND

Float

1001 001

49

GND

V+

1001 010

4A

Float

GND

1001 011

4B

Float

Float

1001 100

4C

Float

V+

1001 101

4D

V+

GND

1001 110

4E

V+

Float

1001 111

4F

V+

V+

1010 000

50

7.5.1.4 Read and Write Operations

Accessing a particular register on the TMP461-SP device is accomplished by writing the appropriate value to the

pointer register. The value for the pointer register is the first byte transferred after the slave address byte with the

R/W bit low. Every write operation to the TMP461-SP device requires a value for the pointer register (see

Figure 15).

When reading from the TMP461-SP device, the last value stored in the pointer register by a write operation is

used to determine which register is read by a read operation. To change which register is read for a read

operation, a new value must be written to the pointer register. This transaction is accomplished by issuing a

slave address byte with the R/W bit low, followed by the pointer register byte; no additional data are required.

The master can then generate a start condition and send the slave address byte with the R/W bit high to initiate

the read command; see Figure 16 for details of this sequence.

If repeated reads from the same register are desired, continually sending the pointer register bytes is not

necessary because the TMP461-SP retains the pointer register value until it is changed by the next write

operation. The register bytes are sent MSB first, followed by the LSB. However, to mitigate effects of single-event

upsets and single-event functional interrupts, it is recommended that appropriate value be written to the pointer

register each time a read operation is performed. Relying on the last value stored in the pointer register may

increase the probability of a failed read due to a single event upset.

Terminate read operations by issuing a not-acknowledge command at the end of the last byte to be read. For a

single-byte operation, the master must leave the SDA line high during the acknowledge time of the first byte that

is read from the slave.

7.5.1.5 Timeout Function

The TMP461-SP device resets the serial interface if either SCL or SDA are held low for 25 ms (typical) between

a start and stop condition. If the TMP461-SP device is holding the bus low, the device releases the bus and waits

for a start condition. To avoid activating the timeout function, maintaining a communication speed of at least 1

kHz for the SCL operating frequency is necessary.

7.5.1.6 High-Speed Mode

For the two-wire bus to operate at frequencies above 1 MHz, the master device must issue a high-speed mode

(HS-mode) master code (0000 1xxx) as the first byte after a start condition to switch the bus to high-speed

operation. The TMP461-SP device does not acknowledge this byte, but switches the input filters on SDA and

SCL and the output filter on SDA to operate in HS-mode, thus allowing transfers at up to 2.17 MHz. After the HS-

mode master code is issued, the master transmits a two-wire slave address to initiate a data transfer operation.

The bus continues to operate in HS-mode until a stop condition occurs on the bus. Upon receiving the stop

condition, the TMP461-SP device switches the input and output filters back to fast mode operation.