TLC2933A

HIGH PERFORMANCE PHASE LOCKED LOOP

SLES149 − OCTOBER 2005

7

TI.COM

electrical characteristics, VDD = 3.3 V, TA = 25°C (unless otherwise noted)

VCO section

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOH

High level output voltage

IOH = –2 mA

2.64

V

VOL

Low level output voltage

IOL = 2 mA

0.33

V

VTH

Input threshold voltage at select, VCO inhibit

1.05

1.65

2.25

V

II

Input current at Select, VCO inhibit

VI = VDD or GND

±1

µA

ZI(VCOIN)

VCO IN input impedance

VCO IN = 1/2 VDD

10

M

Ω

IDD(INH)

VCO supply current (inhibit)

See Note 10

0.44

1

µA

IDD(VCO)

VCO supply current

See Note 11

14.7

28

mA

NOTES: 10. Current into VCO VDD, when VCO INHIBIT = high, PFD is inhibited.

11. Current into VCO VDD, when VCO IN = 1/2 VDD, RBIAS = 3.3 kΩ, VCOOUT = 15-pF Load, VCO INHIBIT = GND, and

PFD INHIBIT = GND.

PFD section

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOH

High level output voltage

IOH = –2 mA

2.97

V

VOL

Low level output voltage

IOL = 2 mA

0.2

V

IOZ

High impedance state output current

PFD inhibit = high, VO = VDD or GND

±1

µA

VIH

High level input voltage at Fin−A, Fin−B

2.1

V

VIL

Low level input voltage at Fin−A, Fin−B

0.5

V

VTH

Input threshold voltage at PFD inhibit

1.05

1.65

2.25

CIN

Input capacitance at Fin−A, Fin−B

5.6

pF

ZIN

Input impedance at Fin−A, Fin−B

10

M

Ω

IDD(Z)

High impedance state PFD supply current

See Note 12

1

µA

IDD(PFD)

PFD supply current

See Note 13

3

mA

NOTES: 12. The current into LOGIC VDD when FIN−A and FIN−B = ground, PFD INHIBIT = VDD, PFD OUT open, and VCO OUT is inhibited.

13. The current into LOGIC VDD when FIN−A = 1 MHz and FIN−B = 1 MHz (VI(PP) = 3.3 V, rectangular wave), PFD INHIBIT = GND,

PFD OUT open, and VCO OUT is inhibited.

operation characteristics, VDD = 3.3 V, TA = 25°C (unless otherwise noted)

VCO section

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fOSC

Operation oscillation frequency

RBIAS = 3.3 kΩ, VCO IN = 1/2 VDD

35

55

80

MHz

fstb

Time to stable oscillation (see Note 14)

10

µs

tr

Rise time

CL = 15 pF

8.3

14

ns

tf

Fall time

CL = 15 pF

6.7

12

ns

fDUTY

Duty cycle at VCO OUT

RBIAS = 3.3 kΩ, VCO IN = 1/2 VDD

45%

50%

55%

α (fOSC)

Temperature coefficient of oscillation

frequency

VCO IN = 1/2 VDD, TA = –20°C to 75°C

–0.232

%/

°C

kSVS(fOSC)

Supply voltage coefficient of oscillation

frequency

VCO IN = 1/2 VDD, VDD = 4.75 V to 5.25 V

0.002

%/m

V

Jitter absolute (see Note 15)

PLL jitter, N = 128

211

ps

NOTES: 14. The time period to the stable VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.

15. Jitter performance is highly dependent on circuit layout and external device characteristics. The jitter specification was made with

a carefully deigned PCB with no device socket.