THS8136

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SLES236B – NOVEMBER 2008 – REVISED APRIL 2013

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

AB

45

O

Analog blue current output, capable of directly driving a double terminated 75-

Ω coaxial cable

AG

41

O

Analog green current output, capable of directly driving a double terminated 75-

Ω coaxial cable

AR

43

O

Analog red current output, capable of directly driving a double terminated 75-

Ω coaxial cable

AVDD

40, 44

I

Analog power supply (3.3 V). All AVDD pins must be connected.

AVSS

42, 46

I

Analog ground

SYNC

24

I

Sync insertion input. Active low. When asserted, the G output is forced to the bottom sync tip level.

Connect to DVSS (GND) or logic low to enable bi-level sync insertion. Connect to DVDD (1.8 V) or logic high

SYNC-T

25

I

for generic DAC applications not requiring sync insertion.

Connect to DVSS (GND) or logic 0 for RGB blanking level operation. Connect to the SYNC control input for

M2

48

I

YPbPr video operation.

M1

47

I

Must be tied to DVSS (GND) or logic 0 for normal operation.

B0

10

B1

9

B2

8

B3

7

B4

6

Blue or (Pb) pixel data input. Signals with index 0 denote the least significant bit. Unused inputs should be

I

B5

5

connected to DVSS(GND).

B6

4

B7

3

B8

2

B9

1

Blanking control input, active low. A rising edge on CLK latches BLANK. When asserted, the AR, AG, and AB

BLANK

23

I

outputs are driven to the reference blanking level, regardless of the value on the data inputs.

CLK

26

I

Clock input. A rising edge on CLK latches R0–R9, G0–G9, B0–B9, and BLANK.

COMP

39

O

Compensation terminal. A 0.1-µF capacitor must be connected between COMP and AVDD.

DVDD

12

I

Digital power supply (1.8 V)

DVSS

11

I

Digital ground

Full-scale adjust control. The full-scale current drive on each of the output channels is determined by the

FSADJ

38

I

value of a resistor RFS connected between this terminal and AVSS. Figure 3 shows the relationship between

full-scale output voltage compliance and RFS for the nominal DAC termination of 37.5 Ω.

G0

36

G1

35

G2

34

G3

33

G4

32

Green (or Y) pixel data input. Signals with index 0 denote the least significant bit. Unused inputs should be

I

G5

31

connected to DVSS(GND).

G6

30

G7

29

G8

28

G9

27

R0

13

R1

14

R2

15

R3

16

R4

17

Red (or Pr) pixel data input. Signals with index 0 denote the least significant bit. Unused inputs should be

I

R5

18

connected to DVSS(GND).

R6

19

R7

20

R8

21

R9

22

Voltage reference for DACs. An internal voltage reference of nominally 1.2 V is provided, which requires an

VREF

37

O

external 0.1-µF ceramic capacitor between VREF and AVSS.

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