PCM1740ESLASH2K.B datasheet(11/26 Pages) TI2

11 / 26 page

PCM1740

SBAS128B

www.ti.com

Loss of Synchronization

Ideally, LRCK and BCK will be derived from the SCKO

output, ensuring synchronous operation. For other cases, the

PCM1740 includes circuitry to detect loss of synchroniza-

tion between the LRCK and the system clock, SCKO. A loss

of synchronization condition is detected when the phase

relationship between SCKO and LRCK exceeds

±6 BCK

cycles during one sample period, or 1/fS. If a loss of

synchronization condition is detected, the DAC operation

will halt within one sample period and the analog outputs

will be forced to VCC/2 until re-synchronization between

LRCK and SCKO is completed. Figure 11 shows the state of

the analog outputs given a loss of synchronization event.

During the undefined states, as well as transitions between

normal and undefined states, the analog outputs may gener-

ate audible noise.

USER PROGRAMMABLE FUNCTIONS

The PCM1740 includes a number of programmable func-

tions, which are configured using five control registers.

These registers are accessed using the I2C-Bus interface.

This section describes the control registers, while the

I2C-Bus interface is described in a later section. Table II lists

the available functions and their corresponding reset default

condition.

The control register map is shown in Table III. Sub-address

bits B8 through B10 are used to specify the register that is

being written. All reserved bits, shown as “res”, must be set

to ‘0’.

The following pages provide detailed descriptions of the five

control registers and their associated functions. All reserved

bits, shown as “res”, must be set to ‘0’.

FIGURE 10. Audio Interface Timing.

FIGURE 11. Loss of Synchronization and Analog Output State.

B15

B14

B13

B12

B11

B10

res

AL7

AL6

AL5

AL4

AL3

AL2

AL1

AL0

res

AR7

AR6

AR5

AR4

AR3

AR2

AR1

AR0

res

PL3

PL2

PL1

PL0

IW1

IW0

DEM

MUT

res

SF1

SF0

DSR1

DSR0

SYS

ATC

LRP

IIS

res

OPE

IZD

SUB ADDRESS BYTE

DATA BYTE

TABLE III. Control Register Map.

FUNCTION

MODE BY DEFAULT

Audio Data Format Select:

Standard Format /I2S Format

Standard Format

Audio Data Word Select:

16-Bit /20-Bit /24-Bit

16-Bit

Polarity of LR-clock Selection

Left/Right = HIGH/LOW

De-emphasis Control:

OFF, 32kHz, 44.1kHz, 48kHz

OFF

Soft Mute Control

OFF

Attenuation Data for Left-channel

0dB

Attenuation Data for Right-channel

0dB

Attenuation Data Mode Control

Left-channel, Right-channel Individually

Analog Output Mode Select

Stereo Mode

Infinity Zero Detect Mute Control

OFF

DACs Operation Control

System Clock Select: 256fS/384fS

384fS

Sampling Frequency Select:

32kHz Group, 44.1kHz Group, 48kHz Group

44.1kHz Group

Sampling Frequency Multiplier:

Normal/ Double/ Half

Normal, x1

TABLE II. User-Programmable Functions.

Normal

Synchronous

Asynchronous

within

1/f

Synchronous

Undefined Data

Undefined

Data

COM

(= 0.5 V

CC)

22.2/f

State of

Synchronization

OUT

LRCKIN

BCKIN

DIN

1.4V

BCH

BCL

BCKIN Pulse Cycle Time

BCKIN Pulse Width High

BCKIN Pulse Width Low

BCKIN Rising Edge to LRCIN Edge

LRCIN Edge to BCKIN Rising Edge

DIN Set-up Time

DIN Hold Time

: t

BCY

: t

BCH

: t

BCL

: t

: 100ns (min)

: 50ns (min)

: 30ns (min)

BCY

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