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LAN9252V/ML датащи(PDF) 172 Page - Microchip Technology

номер детали LAN9252V/ML
подробное описание детали  2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs
PDF  329 Pages
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производитель  MICROCHIP [Microchip Technology]
домашняя страница  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9252V/ML датащи(HTML) 172 Page - Microchip Technology

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LAN9252
DS00001909A-page 172
 2015 Microchip Technology Inc.
11.2.16.21 PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x)
This read/write register is used to enable or mask the various PHY interrupts and is used in conjunction with the PHY x
Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x).
Index (decimal): 30
Size:
16 bits
Bits
Description
Type
Default
15:10
RESERVED
RO
-
9
INT9_MASK
This interrupt mask bit enables/masks the Link Up (link status asserted) inter-
rupt.
0: Interrupt source is masked
1: Interrupt source is enabled
R/W
0b
8
INT8_MASK
This interrupt mask bit enables/masks the WoL interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
R/W
0b
7
INT7_MASK
This interrupt mask bit enables/masks the ENERGYON interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
R/W
0b
6
INT6_MASK
This interrupt mask bit enables/masks the Auto-Negotiation interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
R/W
0b
5
INT5_MASK
This interrupt mask bit enables/masks the remote fault interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
R/W
0b
4
INT4_MASK
This interrupt mask bit enables/masks the Link Down (link status negated)
interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
R/W
0b
3
INT3_MASK
This interrupt mask bit enables/masks the Auto-Negotiation LP acknowledge
interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
R/W
0b



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