LAN9252VSLASHML datasheet(170/329 Pages) MICROCHIP

170 / 329 page

LAN9252

DS00001909A-page 170

 2015 Microchip Technology Inc.

11.2.16.20 PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x)

This read-only register is used to determine to source of various PHY interrupts. All interrupt source bits in this register

are read-only and latch high upon detection of the corresponding interrupt (if enabled). A read of this register clears the

interrupts. These interrupts are enabled or masked via the PHY x Interrupt Mask Register (PHY_INTER-

RUPT_MASK_x).

Index (decimal): 29

Size:

16 bits

Bits

Description

Type

Default

15:9

RESERVED

INT9

This interrupt source bit indicates a Link Up (link status asserted).

0: Not source of interrupt

1: Link Up (link status asserted)

RO/LH

INT8

0: Not source of interrupt

1: Wake on LAN (WoL) event detected

RO/LH

INT7

This interrupt source bit indicates when the Energy On (ENERGYON) bit of

the PHY x Mode Control/Status Register (PHY_MODE_CONTROL_STA-

TUS_x) has been set.

0: Not source of interrupt

1: ENERGYON generated

RO/LH

INT6

This interrupt source bit indicates Auto-Negotiation is complete.

0: Not source of interrupt

1: Auto-Negotiation complete

RO/LH

INT5

This interrupt source bit indicates a remote fault has been detected.

0: Not source of interrupt

1: Remote fault detected

RO/LH

INT4

This interrupt source bit indicates a Link Down (link status negated).

0: Not source of interrupt

1: Link Down (link status negated)

RO/LH

INT3

This interrupt source bit indicates an Auto-Negotiation LP acknowledge.

0: Not source of interrupt

1: Auto-Negotiation LP acknowledge

RO/LH

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