SYSTEM CLOCK INPUT

tw(SCKH)

System Clock

tw(SCKL)

2 V

0.8 V

H

L

System Clock

Pulse Cycle

Time(1)

T0005A08

PCM1680

SLES133B – MARCH 2005 – REVISED OCTOBER 2008.................................................................................................................................................. www.ti.com

The PCM1680 requires a system clock for operating the digital interpolation filters and multilevel

ΔΣ modulators.

The system clock is applied at the SCK (pin 5) input. Table 1 shows examples of system clock frequencies for

common audio sampling rates.

Figure 20 shows the timing requirements for the system clock input. For optimal performance, it is important to

use a clock source with low phase jitter and noise. Texas Instruments’ PLL170x multi-clock generator is an

excellent choice for providing the PCM1680 system clock source.

Table 1. System Clock Frequencies for Common Audio Sampling Frequencies

SAMPLING

SYSTEM CLOCK FREQUENCY (fSCK), MHz

FREQUENCY

128 fS

192 fS

256 fS

384 fS

512 fS

768 fS

1152 fS

8 kHz

1.024

1.536

2.048

3.072

4.096

6.144

9.216

16 kHz

2.048

3.072

4.096

6.144

8.192

12.288

18.432

32 kHz

4.096

6.144

8.192

12.288

16.384

24.576

36.864

44.1 kHz

5.6448

8.4672

11.2896

16.9344

22.5792

33.8688

—(1)

48 kHz

6.144

9.216

12.288

18.432

24.576

36.864

—(1)

88.2 kHz

11.2896

16.9344

22.5792

33.8688

—(1)

—(1)

—(1)

96 kHz

12.288

18.432

24.576

36.864

—(1)

—(1)

—(1)

192 kHz

24.576

36.864

—(1)

—(1)

—(1)

—(1)

—(1)

(1)

This system clock frequency is not supported for the given sampling frequency.

(1) 1/128 fS, 1/192 fS, 1/256 fS, 1/384 fS, 1/512 fS, 1/768 fS, or 1/1152 fS.

PARAMETER

MIN

MAX

UNIT

tw(SCKH)

System clock pulse duration, HIGH

7

ns

tw(SCKL)

System clock pulse duration, LOW

7

ns

Figure 20. System Clock Timing

12

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