LP3992

SNVS192C – OCTOBER 2002 – REVISED NOVEMBER 2015

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Another important consideration is that tantalum capacitors have higher ESR values than equivalent size

ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the

stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic

capacitor with the same ESR value. Also, the ESR of a typical tantalum increases about 2:1 as the temperature

goes from 25°C down to –40°C, so some guard band must be allowed.

9.2.2.6 Power Dissipation

The permissible power dissipation for any package is a measure of the capability of the device to pass heat from

the power source, the junctions of the device, to the ultimate heat sink, the ambient environment. Thus, the

power dissipation is dependent on the ambient temperature and the thermal resistance across the various

interfaces between the die and ambient air (see Equation 1).

TA(MAX) = TJ(MAX-OP) − (PD(MAX) × RθJA)

(1)

The allowable power dissipation for the device in a given package can be calculated:

PD = TJ(MAX) – TA / RθJA

(2)

The actual power dissipation across the device can be represented by Equation 3:

PD = (VIN − VOUT) × IOUT

(3)

This establishes the relationship between the power dissipation allowed due to thermal consideration, the voltage

drop across the device, and the continuous current capability of the device. Equation 2 and Equation 3 must be

used to determine the optimum operating conditions for the device in the application.

This thermal resistance (RθJA) is highly dependent on the heat-spreading capability of the particular PCB design

and therefore varies according to the total copper area, copper weight, and location of the planes. The RθJA

recorded in Thermal Information is determined by the specific EIA/JEDEC JESD51-7 standard for PCB and

copper-spreading area and is to be used only as a relative measure of package thermal performance. For a well-

designed thermal layout, RθJA is actually the sum of the SOT-23 package junction-to-board thermal resistance

(RθJB) plus the thermal resistance contribution by the PCB copper area acting as a heatsink.

9.2.2.7 Estimating Junction Temperature

The EIA/JEDEC standard recommends the use of psi (

Ψ) thermal characteristics to estimate the junction

temperatures of surface mount devices on a typical PCB board application. These characteristics are not true

thermal resistance values, but rather package specific thermal characteristics that offer practical and relative

means of estimating junction temperatures. These psi metrics are determined to be significantly independent of

copper-spreading area. The key thermal characteristics (

ΨJT and ΨJB) are given in Thermal Information and are

used in accordance with Equation 4 or Equation 5.

TJ(MAX) = TTOP + (ΨJT × PD(MAX))

where

•

PD(MAX) is explained in Equation 2

•

TTOP is the temperature measured at the center-top of the device package.

(4)

TJ(MAX) = TBOARD + (ΨJB × PD(MAX))

where

•

PD(MAX) is explained in Equation 2.

•

TBOARD is the PCB surface temperature measured 1-mm from the device package and centered on the

package edge.

(5)

For more information about the thermal characteristics

ΨJT and ΨJB, see TI Application Report Semiconductor

and IC Package Thermal Metrics (SPRA953); for more information about measuring TTOP and TBOARD, see the TI

Application Report Using New Thermal Metrics (SBVA025); and for more information about the EIA/JEDEC

JESD51 PCB used for validating RθJA, see the TI Application Report Thermal Characteristics of Linear and Logic

Packages Using JEDEC PCB Designs (SZZA017). Aforementioned application notes are available at

www.ti.com.

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