R/W

S

Slave Address

(7 bits)

'0' A

A

A P

Control Register Add.

(8 bits)

(8 bits)

Register Data

Data transferred, byte +

Ack

A - ACKNOWLEDGE (SDA Low)

S - START CONDITION

P - STOP CONDITION

From Slave to Master

From Master to Slave

LP3918

www.ti.com

SNVS476D – AUGUST 2007 – REVISED MAY 2013

•

Write cycle ends when the master creates stop condition.

CONTROL REGISTER READ CYCLE

•

Master device generates a start condition.

•

Master device sends slave address (7 bits) and the data direction bit (r/w = “0”).

•

Slave device sends acknowledge signal if the slave address is correct.

•

Master sends control register address (8 bits).

•

Slave sends acknowledge signal.

•

Master device generates repeated start condition.

•

Master sends the slave address (7 bits) and the data direction bit (r/w = “1”).

•

Slave sends acknowledge signal if the slave address is correct.

•

Slave sends data byte from addressed register.

•

If the master device sends acknowledge signal, the control register address will be incremented by one. Slave

device sends data byte from addressed register.

•

Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop

condition.

Address Mode(1)

Data Read

<Start Condition>

<Slave Address><r/w = ‘0’>[Ack]

<Register Addr.>[Ack]

<Repeated Start Condition>

<Slave Address><r/w = ‘1’>[Ack]

[Register Date]<Ack or nAck>

… additional reads from subsequent register address possible

<Stop Condition>

Data Write

<Start Condition>

<Slave Address><r/w = ‘0’>[Ack]

<Register Addr.>[Ack]

<Register Data>[Ack]

… additional writes to subsequent register address possible

<Stop Condition>

(1)

< > Data from master [ ] Data from slave

REGISTER READ AND WRITE DETAIL

Figure 17. Register Write Format

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