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LP3918TL/NOPB датащи(PDF) 18 Page - Texas Instruments |
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LP3918TL/NOPB датащи(HTML) 18 Page - Texas Instruments |
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18 / 38 page ![]() PS_HOLD RESET 1.2s HF_PWR CHG_IN 320 ms PS_HOLD needs to be asserted within 1200 ms after CHG_IN or HF_PWR rising edge has been detected. (HF_PWR level detected for LP3918TL-C) Note: Serial I/F commands only take place after PS_HOLD is asserted. PS_HOLD high < 1.2s from I/P detection If charger is connected (CHG_IN) or HF_PWR is applied, then both events are filtered for 320 ms before enabling LDO1 Debounce time before normal start up sequence, 320 ms. 60 ms 87% Reg 87% Reg I2C Control < 200 Ps LDO4,5,6 LDO7 LDO3 LDO2 LDO1 RX_EN, TX_EN, TCXO_EN LP3918 SNVS476D – AUGUST 2007 – REVISED MAY 2013 www.ti.com Figure 5. Device Power Up Logic Timing. CHG_IN, HF_PWR 18 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP3918 |
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