AD5066 datasheet(12/20 Pages) AD

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AD5066

Preliminary Technical Data

Rev. PrB | Page 12 of 20

THEORY OF OPERATION

D/A SECTION

The AD5066 are Quad 16-bit, serial input, voltage output

DACs. The parts operate from supply voltages of 2.7 V to 5.5 V.

Data is written to the AD5066 in a 32-bit word format via a 3-

wire serial interface. The AD5066 incorporates a power-on reset

circuit that ensures the DAC output powers up to a known out-

put state (midscale or zero-scale, see the Ordering Guide). The

devices also have a software power-down mode that reduces the

typical current consumption to less than 1 μa.

Because the input coding to the DAC is straight binary, the ideal

output voltage when using an external reference is given by

⎟

⎠

⎞

⎜

⎝

⎛

REFIN

OUT

The ideal output voltage when using and internal reference is

given by

⎟

⎠

⎞

⎜

⎝

⎛

REFOUT

OUT

where:

= decimal equivalent of the binary code that is loaded to the

DAC register. 0 to 65,535 for AD5066 (16 bits).N = the DAC

resolution.

DAC ARCHITECTURE

The DAC architecture of the AD5066 consists of two matched

DAC sections. A simplified circuit diagram is shown in Figure

5. The four MSBs of the 16-bit data word are decoded to drive

15 switches, E1 to E15. Each of these switches connects one of

15 matched resistors to either GND or VREF

buffer output. The

remaining 12 bits of the data word drive switches S0 to S11 of a

12-bit voltage mode R-2R ladder network.

VREF

S11

E15

VOUT

12-BIT R-2R LADDER

FOUR MSBs DECODED INTO

15 EQUAL SEGMENTS

Figure 6. Dac Ladder Structure

REFERENCE BUFFER

The AD5066 operates with an external reference. Each of the

four onboard dac’s will have a dedicated voltage reference pin.

In either case the reference input pin has an input range of 2 V

to VDD. This input voltage is then used to provide a buffered

reference for the DAC core.

TO OUTPUT

AMPLIFIER

Figure 7. Resistor String

SERIAL INTERFACE

The AD5066 has a 3-wire serial interface (SYNC, SCLK, and

DIN) that is compatible with SPI, QSPI, and MICROWIRE

interface standards as well as most DSPs. See Figure 3 for a

timing diagram of a typical write sequence.

STANDALONE MODE

The write sequence begins by bringing the SYNC line low. Data

from the DIN line is clocked into the 32-bit shift register on the

falling edge of SCLK. The serial clock frequency can be as high

as 50 MHz, making the AD5066 compatible with high speed

DSPs. On the 32nd falling clock edge, the last data bit is clocked

in and the programmed function is executed, that is, a change

in DAC register contents and/or a change in the mode of

operation. At this stage, the SYNC line can be kept low or be

brought high. In either case, it must be brought high for a

minimum of 15 ns before the next write sequence so that a

falling edge of SYNC can initiate the next write sequence.

Because the SYNC buffer draws more current when VIN = 2 V

than it does when VIN = 0.8 V, SYNC should be idled low

between write sequences for even lower power operation of the

part. As is mentioned previously, however, SYNC must be

brought high again just before the next write sequence.

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