DATA (3)

MOSI

DATA (1)

DATA (2)

72 Clock Cycles

CSB

LMP92018

SNAS514B – NOVEMBER 2011 – REVISED MAY 2013

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A typical bus cycle for this scheme is initiated by the falling CSB. After the 24 SCLK cycles new data starts to

appear at the DOUT pin of the first device in the chain, and starts shifting into the second device. After the 72

SCLK cycles following the falling CSB edge, all three devices in this example will contain new data in their input

shift registers. Raising CSB will begin the process of decoding data in each device. When in the Daisy Chain the

full READ and WRITE capability of every device is maintained.

A sample of SPI data transfer appropriate for a 3 device Daisy Chain is shown in Figure 27.

Figure 27. SPI Daisy Chain Transaction

26

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