LMP92018

SNAS514B – NOVEMBER 2011 – REVISED MAY 2013

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x

Don't Care

Each bit will be forced at the corresponding GPIO pin of the device. Bits corresponding to GPIO pins configured as inputs

CGPO

will be ignored. CGPO[11:0]=0x000

VENDOR ID

The 16–bit ID sequence is factory set, and can only be tested via the SPI transaction shown in the table below.

FRAME 1: DIN

FRAME 2: DOUT

Command

Payload

Command

Payload

Bit

→

23

22:16

15:0

23

22:16

15:0

READ

1

1000000

x

1

1000000

ID

x

Don't Care

ID

Vendor ID number. ID = 0x0028.

VERSION/STEPPING

Version and Stepping words are factory set and can only be tested via the SPI transaction shown in the table

below.

FRAME 1: DIN

FRAME 2: DOUT

Command

Payload

Command

Payload

Bit

→

23

22:16

15:4

3:0

23

22:16

15:4

3:0

READ

1

1000001

x

x

1

1000001

VER

STEP

x

Don't Care

VER

Indicates the device version number. VER=0x000

STEP

Indicates stepping number. STEP = 0x0

DAC DATA REGISTER ACCESS

Each DAC's input data register, DDATA, is individually addressable, and its contents can be updated without

affecting remaining 3 DACs. The content of each DDATA can be tested and set via the SPI transactions shown

in the following table. The DAC block is described in PROGRAMMABLE ANALOG OUTPUT SUBSYSTEM.

FRAME 1: DIN

FRAME 2: DOUT

Command

Payload

Command

Payload

Bit

→

23

22:18

17:16

15:12

11:2

1:0

23

22:18

17:16

15:12

11:2

1:0

READ

1

10100

ADR

x

x

x

1

10100

ADR

0000

DDATA

00

WRITE

0

10100

ADR

0000

DDATA

00

0

10100

ADR

0000

10'b0

00

x

Don't Care

DAC address:

00: DAC0

ADR

01: DAC1

10: DAC2

11: DAC3

DDATA

DAC input data. DDATA is a 10–bit unsigned integer. DDATA=0x000

16

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