LMP91000

µC

SCL

SDA

GPIO 1

GPIO 2

GPIO 3

GPIO N

LMP91000

LMP91000

LMP91000

D7

D6

D5

D4

D3

D2

D1

D0

1

9

Ack

by

LMP91000

Start by

Master

No Ack

by

Master

SCL

SDA

Stop

by

Master

1

9

Frame 1

Serial Bus Address Byte

from Master

Frame 2

Data Byte from

Slave

R/W

A2

A0

A1

A3

A4

A5

A6

MENB

D7

D6

D5

D4

D3

D2

D1

D0

1

9

1

9

Ack

by

LMP91000

Start by

Master

R/W

Ack

by

LMP91000

Frame 1

Serial Bus Address Byte

from Master

Frame 2

Internal Address Register

Byte from Master

A2

A0

A1

A3

A4

A5

A6

SCL

SDA

Stop by

Master

MENB

LMP91002

www.ti.com

SNIS163B – APRIL 2012 – REVISED OCTOBER 2015

Programming (continued)

Figure 14. (b) Pointer Set Transaction

(c) Register read transaction

Figure 15. READ and WRITE Transaction

7.5.3 Connection of More Than One LMP91002 to the I2C Bus

The LMP91002 comes out with a unique and fixed I2C slave address. It is still possible to connect more than one

LMP91002 to an I2C bus and select each device using the MENB pin. The MENB simply enables/disables the

I2C communication of the LMP91002. When the MENB is at logic level low all the I2C communication is enabled,

it is disabled when MENB is at high logic level.

In a system based on a

μcontroller and more than one LMP91002 connected to the I2C bus, the I2C lines (SDA

and SCL) are shared, while the MENB of each LMP91002 is connected to a dedicate GPIO port of the

μcontroller.

The

μcontroller starts communication asserting one out of N MENB signals where N is the total number of

LMP91002s connected to the I2C bus. Only the enabled device will acknowledge the I2C commands. After

finishing communicating with this particular LMP91002, the microcontroller de-asserts the corresponding MENB

and repeats the procedure for other LMP91002s. Figure 16 shows the typical connection when more than one

LMP91002 is connected to the I2C bus.

Figure 16. More than one LMP91002 on I2C bus

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