SMBP2501BPB datasheet(21/107 Pages) SONIX

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SN8P2501B

8-Bit Micro-Controller

SONiX TECHNOLOGY CO., LTD

Page 21

Version 2.1

2.1.2 CODE OPTION TABLE

Code Option

Content

Function Dsecription

Noise_Filter

Enable

Enable Noise Filter and the Fcpu is Fosc/4~Fosc/16.

Disable

Disable Noise Filter and the Fcpu is Fosc/1~Fosc/16.

Fcpu

Fhosc/1

Instruction cycle is oscillator clock.

Notice: In Fosc/1, Noise Filter must be disabled.

IHRC_16M and IHRC_RTC modes don't support Fosc/1.

Fhosc/2

Instruction cycle is 2 oscillator clocks.

Notice: In Fosc/2, Noise Filter must be disabled.

IHRC_16M and IHRC_RTC modes don't support Fosc/2.

Fhosc/4

Instruction cycle is 4 oscillator clocks.

Fhosc/8

Instruction cycle is 8 oscillator clocks.

Fhosc/16

Instruction cycle is 16 oscillator clocks.

High_Clk

IHRC_16M

High speed internal 16MHz RC. XIN/XOUT become to P1.3/P1.2

bi-direction I/O pins.

Fcpu range is Fosc/4~Fosc/16 in IHRC_16M .

IHRC_RTC

High speed internal 16MHz RC with 0.5sec RTC. XIN/XOUT pins connect

with 32768Hz crystal for RTC clock source.

Fcpu range is Fosc/4~Fosc/16 in IHRC_RTC .

Low cost RC for external high clock oscillator and XOUT becomes to P1.2

bit-direction I/O pin.

32K X’tal

Low frequency, power saving crystal (e.g. 32.768KHz) for external high

clock oscillator.

12M X’tal

High speed crystal /resonator (e.g. 12MHz) for external high clock

oscillator.

4M X’tal

Standard crystal /resonator (e.g. 4M) for external high clock oscillator.

Watch_Dog

Always_On

Watchdog timer is always on enable even in power down and green

mode.

Enable

Enable watchdog timer. Watchdog timer stops in power down mode and

green mode.

Disable

Disable Watchdog function.

Reset_Pin

Reset

Enable External reset pin.

P11

Enable P1.1 input only without pull-up resister.

LVD

LVD_L

LVD will reset chip if VDD is below 2.0V

LVD_M

LVD will reset chip if VDD is below 2.0V

Enable LVD24 bit of PFLAG register for 2.4V low voltage indicator.

LVD_H

LVD will reset chip if VDD is below 2.4V

Enable LVD36 bit of PFLAG register for 3.6V low voltage indicator.

Security

Enable

Enable ROM code Security function.

Disable

Disable ROM code Security function.



Note:

In high noisy environment, enable “Noise Filter” and set Watch_Dog as “Always_On”

is strongly recommended. Enable

“Noise_Filter” will limit the Fcpu = Fosc/4 ~ Fosc/16.

If users define watchdog as

“Always_On”, assembler will Enable “Watch_Dog”

automatically.

Fcpu code option is only available for High Clock. Fcpu of slow mode is Fosc/4 (the

Fosc is internal low clock).

In IHRC_16M and IHRC_RTC modes, the Fcpu is Fosc/4~Fosc.16.

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