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ISO7421 датащи(PDF) 11 Page - Texas Instruments

номер детали ISO7421
подробное описание детали  ISO7421-EP Low-Power Dual Digital Isolators
PDF  25 Pages
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производитель  TI2 [Texas Instruments]
домашняя страница  https://www.ti.com
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ISO7421 датащи(HTML) 11 Page - Texas Instruments

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ISO7421-EP
www.ti.com
SLLSEN3 – DECEMBER 2015
8.3 Feature Description
8.3.1 Insulation Characteristics
Over recommended operating conditions (unless otherwise noted)
PARAMETER(1)
TEST CONDITIONS
SPECIFICATION
UNIT
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM
Maximum working insulation voltage
566
VPK
VPR
Input-to-output test voltage
t = 1 s (100% production), partial discharge 5 pC
1062
VPK
t = 60 s (qualification)
VIOTM
Transient overvoltage
4242
VPK
t = 1 s (100% production)
RS
Insulation resistance
VIO = 500 V at TS
>109
Pollution degree
2
UL 1577
VTEST = VISO = 2500 VRMS, t = 60 s (qualification)
VISO
Isolation voltage per UL
2500
VRMS
VTEST = 1.2 x VISO = 3000 VRMS, t = 1 s (100%
production)
(1)
Climatic Classification 40/125/21
Table 1. IEC 60664-1 Ratings Table
PARAMETER
TEST CONDITIONS
SPECIFICATION
Material group
II
Rated mains voltage
≤ 150 VRMS
I–IV
Installation classification
Rated mains voltage
≤ 300 VRMS
I–III
8.3.2 Package Characteristics
Over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
L(I01)
Minimum air gap (clearance)
Shortest terminal-to-terminal distance through air
4
mm
Minimum external tracking
Shortest terminal-to-terminal distance across the
L(I02)
4
mm
(creepage)
package surface
Tracking resistance (comparative
CTI
DIN EN 60112 (VDE 0303-11); IEC 60112
>400
V
tracking index)
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
0.014
mm
VIO = 500 V, TA = 25°C
>1012
Isolation resistance, input to
RIO
output(1)
VIO = 500 V, 100°C ≤ TA ≤ max
>1011
Barrier capacitance, input to
CIO
VIO = 0.4 sin (2πft), f = 1 MHz
1
pF
output(1)
CI
Input capacitance(2)
VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V
1
pF
(1)
All pins on each side of the barrier tied together creating a two-terminal device.
(2)
Measured from input pin to ground.
Copyright © 2015, Texas Instruments Incorporated
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