WM8994ECSSLASHR datasheet(357/363 Pages) CIRRUS

357 / 363 page

WM8994

Rev 4.6

357

DIGITAL AUDIO INTERFACE CLOCKING CONFIGURATIONS

The WM8994 provides 3 digital audio interfaces and supports many different clocking configurations.

The asynchronous sample rate converter enables more than one digital audio interface to be

supported simultaneously, even when there is no synchronisation between these interfaces. In a

typical application, this enables audio mixing between a multimedia applications processor and a

baseband voice call processor, for example.

The AIF1 and AIF2 audio interfaces can be configured in Master or Slave modes, and can also

support defined combinations of mixed sample rates. In all applications, it is important that the system

clocking configuration is correctly designed. Incorrect clock configurations will lead to audible clicks

arising from dropped or repeated audio samples; this is caused by the inherent tolerances of multiple

asynchronous system clocks.

To ensure reliable clocking of the audio interface functions, it is a requirement that, for each audio

interface, the external interface clocks (eg. BCLK, LRCLK) are derived from the same clock source as

the respective AIF clock (AIFnCLK).

In AIF Master mode, the external BCLK and LRCLK signals are generated by the WM8994 and

synchronisation of these signals with AIFnCLK is guaranteed. In this case, clocking of the AIF is

derived from the MCLK1 or MCLK2 inputs, either directly or via one of the Frequency Locked Loop

(FLL) circuits.

In AIF Slave mode, the external BCLK and LRCLK signals are generated by another device, as inputs

to the WM8994. In this case, it must be ensured that the respective AIF clock is generated from a

source that is synchronised to the external BCLK and LRCLK inputs. In a typical Slave mode

application, the BCLK input is selected as the clock reference, using the FLL to perform frequency

shifting. It is also possible to use the MCLK1 or MCLK2 inputs, but only if the selected clock is

synchronised externally to the BCLK and LRCLK inputs.

The valid AIF clocking configurations are listed in Table 149 for AIF Master and AIF Slave modes.

AUDIO INTERFACE MODE

CLOCKING CONFIGURATION

AIF Master Mode

AIFnCLK_SRC selects FLL1 or FLL2 as AIFnCLK source;

FLLn_REFCLK_SRC selects MCLK1 or MCLK2 as FLLn source.

AIFnCLK_SRC selects MCLK1 or MCLK2 as AIFnCLK source.

AIF Slave Mode

AIFnCLK_SRC selects FLL1 or FLL2 as AIFnCLK source;

FLLn_REFCLK_SRC selects BCLKn as FLLn source.

AIFnCLK_SRC selects MCLK1 or MCLK2 as AIFnCLK source,

provided MCLK is externally synchronised to the BCLKn input.

AIFnCLK_SRC selects FLL1 or FLL2 as AIFnCLK source;

FLLn_REFCLK_SRC selects MCLK1 or MCLK2 as FLLn source,

provided MCLK is externally synchronised to the BCLKn input.

Table 149 Audio Interface Clocking Confgurations

In each case, the AIFnCLK frequency must be a valid ratio to the LRCLKn frequency; the supported

clocking ratios are defined by the AIFnCLK_RATE register.

The valid AIF clocking configurations are illustrated in Figure 95 to Figure 99 below. Note that, where

MCLK1 is illustrated as the clock source, it is equally possible to select MCLK2 as the clock source.

Similarly, in cases where FLL1 is illustrated, it is equally possible to select the FLL2.

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