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WM8994ECS/R датащи(PDF) 242 Page - Cirrus Logic

номер детали WM8994ECS/R
подробное описание детали  Multi-channel Audio Hub CODEC for Smartphones
PDF  363 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8994ECS/R датащи(HTML) 242 Page - Cirrus Logic

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WM8994
242
Rev 4.6
DCVDD
0V
AVDD2
0V
Vpora
Vpord_off
LO
HI
Internal POR
Device ready
Vpora_on
POR active
POR active
POR undefined
Figure 86 Power On Reset Timing - DCVDD enabled/disabled first
The POR
¯¯¯ signal is undefined until AVDD2 has exceeded the minimum threshold, Vpora. Once this
threshold has been exceeded, POR
¯¯¯ is asserted low and the chip is held in reset. In this condition, all
writes to the control interface are ignored. Once AVDD2 and DCVDD have reached their respective
power on thresholds, POR
¯¯¯ is released high, all registers are in their default state, and writes to the
control interface may take place.
Note that a power-on reset period, TPOR, applies after AVDD2 and DCVDD have reached their
respective power on thresholds. This specification is guaranteed by design rather than test.
On power down, POR
¯¯¯ is asserted low when either AVDD2 or DCVDD falls below their respective
power-down thresholds.
Typical Power-On Reset parameters for the WM8994 are defined in Table 140.
SYMBOL
DESCRIPTION
TYP
UNIT
Vpora_on
Power-On threshold (AVDD2)
1.15
V
Vpora_off
Power-Off threshold (AVDD2)
1.14
V
Vpord_on
Power-On threshold (DCVDD)
0.56
V
Vpord_off
Power-Off threshold (DCVDD)
0.55
V
TPOR
Minimum Power-On Reset period
100
ns
Table 140 Typical Power-On Reset Parameters



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