WM8994ECSSLASHR datasheet(203/363 Pages) CIRRUS

203 / 363 page

WM8994

Rev 4.6

203

The value of FLLn_FRATIO should be selected as described in Table 111.

REFERENCE FREQUENCY FREF

FLLn_FRATIO

1MHz - 13.5MHz

0h (divide by 1)

256kHz - 1MHz

1h (divide by 2)

128kHz - 256kHz

2h (divide by 4)

64kHz - 128kHz

3h (divide by 8)

Less than 64kHz

4h (divide by 16)

Table 111 Selection of FLLn_FRATIO

In order to determine the remaining FLL parameters, the FLL operating frequency, FVCO, must be

calculated, as given by the following equation:

FVCO = (FOUT x FLLn_OUTDIV)

The value of FLLn_N and FLLn_K can then be determined as follows:

N.K = FVCO / (FLLn_FRATIO x FREF)

Note that FREF is the input frequency, after division by FLLn_REFCLK_DIV, where applicable.

In FLL Fractional Mode, the fractional portion of the N.K multiplier is held in the FLLn_K register field.

This field is coded as a fixed point quantity, where the MSB has a weighting of 0.5. Note that, if

desired, the value of this field may be calculated by multiplying K by 216 and treating FLLn_K as an

integer value, as illustrated in the following example:

If N.K = 8.192, then K = 0.192

Multiplying K by 216 gives 0.192 x 65536 = 12582.912 (decimal)

Apply rounding to the nearest integer = 12583 (decimal) = 3127 (hex)

Note that, if the required fraction cannot be represented exactly in the FLL_K register, and a rounding

error is introduced, then a corresponding offset will exist in the FLL output frequency. In a typical

application, the frequency difference will be negligible. However, if the FLL is used to generate

AIFnCLK in AIF Slave Mode, then the rounding error may result in clicks arising from dropped or

repeated audio samples.

The FLL1 control registers are described in Table 112. The FLL2 control registers are described in

Table 113. Example settings for a variety of reference frequencies and output frequencies are shown

in Table 115.

WM8994ECS/R датащи(PDF) 203 Page - Cirrus Logic