WM8994ECSSLASHR datasheet(192/363 Pages) CIRRUS

192 / 363 page

WM8994

192

Rev 4.6

The AIFnCLK / fs ratio is the ratio of AIFnCLK to the AIFn

sample rate, where ‘n’ identifies the

applicable audio interface AIF1 or AIF2. The AIF clocking ratio and sample rate are set by the

AIFnCLK_RATE and AIFn_SR register fields, defined in Table 106 and Table 108.

Note that, in the case of mixed input/output path sample rates on either interface, then

AIFnCLK_RATE and AIFn_SR are set according to the higher of the two sample rates.

The clocking configuration for AIF1CLK, AIF2CLK and SYSCLK is illustrated in Figure 67.

The WM8994 provides integrated pull-up and pull-down resistors on the MCLK1 pin. This provides a

flexible capability for interfacing with other devices. This is configured as described in Table 109. Note

that if MCLK1_PU and MCLK1_PD are both set, then the pull-up and pull-down will be disabled.

GPIO2/MCLK2

MCLK1

FLL2

AIF1CLK_SRC

AIF2CLK_SRC

FLL1

SYSCLK_SRC

AIF1CLK

SYSCLK

AIF2CLK

AIF1CLK_ENA

AIF1CLK_DIV

f/N

AIF2CLK_ENA

AIF2CLK_DIV

f/N

Figure 67 Audio Interface Clock Control

AIF1CLK ENABLE

The AIF1CLK_SRC register is used to select the AIF1CLK source. The source may be MCLK1,

MCLK2, FLL1 or FLL2. If either of the Frequency Locked Loops is selected as the source, then the

FLL(s) must be enabled and configured as described later.

The AIF1CLK clock may be adjusted by the AIF1CLK_DIV divider, which provides a divide-by-two

option. The selected source may also be inverted by setting the AIF1CLK_INV bit.

The maximum AIF1CLK frequency is specified in the “Electrical Characteristics” section. Note that,

when AIF1CLK_DIV = 1, the maximum frequency limit applies to the divided-down AIF1CLK

frequency.

The AIF1CLK is enabled by the register bit AIF1CLK_ENA. This bit should be set to 0 when

reconfiguring the clock sources. It is not recommended to change AIF1CLK_SRC while the

AIF1CLK_ENA bit is set.

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