SCLK

SCSb

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

R/Wb

A3

A2

A1

A0

0

0

0

D7

D6

D5

D4

D3

D2

D1

D0

C7

C6

C5

C4

C3

C2

C1

C0

Reserved (3-bits)

(MSB)

(LSB)

COMMAND FIELD

DATA FIELD

Address (4-bits)

Write DATA

SDI

SDO

Hi-Z

D7

D6

D5

D4

D3

D2

D1

D0

(MSB)

(LSB)

Data (8-bits)

Read DATA

Single Access Cycle

ADC12DS080

SNAS443A – MARCH 2008 – REVISED MARCH 2013

www.ti.com

Figure 24. Serial Interface Protocol

SCLK: Used to register the input data (SDI) on the rising edge; and to source the output data (SDO) on the

falling edge. User may disable clock and hold it in the low-state, as long as clock pulse-width min spec is not

violated when clock is enabled or disabled.

SCSb: Serial Interface Chip Select. Each assertion starts a new register access - i.e., the SDATA field protocol is

required. The user is required to deassert this signal after the 16th clock. If the SCSb is deasserted before the

16th clock, no address or data write will occur. The rising edge captures the address just shifted-in and, in the

case of a write operation, writes the addressed register. There is a minimum pulse-width requirement for the

deasserted pulse - which is specified in the Electrical Specifications section.

SDI: Serial Data. Must observe setup/hold requirements with respect to the SCLK. Each cycle is 16-bits long.

R/Wb:

A value of '1' indicates a read operation, while a value of '0' indicates a write operation.

Reserved:

Reserved for future use. Must be set to 0.

ADDR:

Up to 3 registers can be addressed.

DATA:

In a write operation the value in this field will be written to the register addressed in this cycle when SCSb is

deasserted. In a read operation this field is ignored.

24

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