ADC12DS080

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SNAS443A – MARCH 2008 – REVISED MARCH 2013

Clock Input

The CLK controls the timing of the sampling process. To achieve the optimum noise performance, the clock input

should be driven with a stable, low jitter clock signal in the range indicated in the Electrical Table. The clock input

signal should also have a short transition region. This can be achieved by passing a low-jitter sinusoidal clock

source through a high speed buffer gate. The trace carrying the clock signal should be as short as possible and

should not cross any other signal line, analog or digital, not even at 90°.

The clock signal also drives an internal state machine. If the clock is interrupted, or its frequency is too low, the

charge on the internal capacitors can dissipate to the point where the accuracy of the output data will degrade.

This is what limits the minimum sample rate.

The clock line should be terminated at its source in the characteristic impedance of that line. Take care to

maintain a constant clock line impedance throughout the length of the line. Refer to Application Note AN-905

(SNLA035) for information on setting characteristic impedance.

It is highly desirable that the the source driving the ADC clock pins only drive that pin. However, if that source is

used to drive other devices, then each driven pin should be AC terminated with a series RC to ground, such that

the resistor value is equal to the characteristic impedance of the clock line and the capacitor value is

(6)

where tPD is the signal propagation rate down the clock line, "L" is the line length and ZO is the characteristic

impedance of the clock line. This termination should be as close as possible to the ADC clock pin but beyond it

as seen from the clock source. Typical tPD is about 150 ps/inch (60 ps/cm) on FR-4 board material. The units of

"L" and tPD should be the same (inches or centimeters).

The duty cycle of the clock signal can affect the performance of the A/D Converter. Because achieving a precise

duty cycle is difficult, the ADC12DS080 has a Duty Cycle Stabilizer.

Power-Down (PD_A and PD_B)

The PD_A and PD_B pins, when high, hold the respective channel of the ADC12DS080 in a power-down mode

to conserve power when that channel is not being used. The channels may be powered down individually or

together. The data in the pipeline is corrupted while in the power down mode.

The Power Down Mode Exit Cycle time is determined by the value of the components on the reference bypass

pins ( VRP, VCMO and VRN ). These capacitors lose their charge in the Power Down mode and must be recharged

by on-chip circuitry before conversions can be accurate. Smaller capacitor values allow slightly faster recovery

from the power down mode, but can result in a reduction in SNR, SINAD and ENOB performance.

Note: This signal has no effect when SPI_EN is high and the serial control interface is enabled.

Reset_DLL

This pin is normally low. If the input clock frequency is changed abruptly, the internal timing circuits may become

unlocked. Cycle this pin high for 1 microsecond to re-lock the DLL. The DLL will lock in several microseconds

after Reset_DLL is asserted.

DLC

This pin sets the output data configuration. With this signal at logic-1, all data is sourced on a single lane

(SD1_x) for each channel. When this signal is at logic-0, the data is sourced on dual lanes (SD0_x and SD1_x)

for each channel. This simplifies data capture at higher data rates.

Note: This signal has no effect when SPI_EN is high and the SPI interface is enabled.

TEST

When this signal is asserted high, a fixed test pattern (101001100011 msb->lsb) is sourced at the data outputs.

When low, the ADC is in normal operation. The user may specify a custom test pattern via the serial control

interface.

Note: This signal has no effect when SPI_EN is high and the SPI interface is enabled.

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