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F1953 датащи(PDF) 18 Page - Renesas Technology Corp

номер детали F1953
подробное описание детали  6-Bit Digital Step Attenuator, 1MHz to 4000MHz
PDF  22 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

F1953 датащи(HTML) 18 Page - Renesas Technology Corp

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F1912 Datasheet
R35DS0055EU0100 Rev.1.00
Nov 10, 2022
Page 18
Item #
Part Reference
QTY
DESCRIPTION
Mfr. Part #
Mfr.
9
J5, J7
2
CONN HEADER VERT SGL 2 X 1 POS
GOLD
961102-6404-AR
3M
10
J8
1
CONN HEADER VERT SGL 4 X 1 POS
GOLD
961104-6404-AR
3M
11
J6
1
CONN HEADER VERT SGL 8 X 1 POS
GOLD
961108-6404-AR
3M
12
J2, J3, J4
3
Edge Launch SMA (0.250 inch pitch ground,
round)
142-0711-821
Emerson Johnson
13
U1
1
SWITCH 8 POSITION DIP SWITCH
KAT1108E
E-Switch
14
U2
1
DSA
F1912Z
IDT (Renesas)
15
1
Printed Circuit Board (Rev 01)
F1953S EVKit Rev 01
IDT (Renesas)
16
Bill Of Material (Rev 01)
6.
Applications Information
6.1
F1912 Digital Pin Voltage and Resistance Values (Pins Not Connected)
The following table lists the resistance between various pins and ground when no DC power is applied. When
the device is powered up with +5 Volts DC these same pins should have the measured voltage to ground.
Pin
Name
DC Voltage (volts)
Resistance (ohms)
13
VMODE
2.5V
100 kΩ pullup resistor to internally regulated 2.5 V
3, 4, 5
DATA, CLK, LE
2.5V
100 kΩ pullup resistor to internally regulated 2.5 V
6.2
Logic Voltage Applied before Power Supply
Due to on-chip ESD protection circuitry, the VDD supply voltage is required to be present before the logic
voltages can be applied to the logic pins (VMODE, DATA, LE, CLK, D[5:0]). If in the application this is not possible,
then a series resistor of 3kΩ needs to be added in line with each of the logic pins, D0-D3. The other logic pins
(VMODE, DATA, LE, CLK, D4, D5) already have a significant resistor value per the Bill Of Material (BOM). This
resistor limits the current into the logic pin to a safe level when VDD is not present. The resistor should be placed
close to the device to minimize the impact on switching speed due to stray PCB parasitics.
7.
Package Outline Drawings
The package outline drawings are located at the end of this document and are accessible from the Renesas
website. The package information is the most current data available and is subject to change without revision of
this document.



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