F1912 Datasheet

R35DS0055EU0100 Rev.1.00

Nov 10, 2022

Page 10

Figure 2. Serial Register Timing Diagram

Note: When Latch enable is high, the shift register is disabled and DATA is NOT continuously clocked into the

shift register which minimizes noise. It is recommended that Latch enable be left high when the device is not

being programmed.

Table 3. Serial Mode Timing Table

Interval Symbol

Description

Min Spec

Max Spec

Unit

tmc

Parallel to Serial Setup Time - From rising edge of VMODE to rising

edge of CLK for D5

100

ns

tds

Clock high pulse width

10

ns

tcls

LE Setup Time - From the rising edge of CLK pulse for D0 to LE

rising edge minus half the clock period.

10

ns

tlew

LE pulse width

30

ns

tdsc

Data Setup Time - From the starting edge of Data bit to rising edge

of CLK

10

ns

tdht

Data Hold Time - From rising edge of CLK to falling edge of the

Data bit.

10

ns

3.2.2.

Serial Mode Default Startup Condition:

When the device is first powered up it will default to the Maximum Attenuation of 31.5 dB independent of the

VMODE and parallel pin [D5:D0] conditions.

Table 4. Default Control Word for the Serial Mode

D5 (MSB)

D4

D3

D2

D1

D0 (LSB)

Attenuation (dB)

1

1

1

1

1

1

31.5