BM83 datasheet(42/76 Pages) MICROCHIP

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6.2

Reset

The Reset logic generates proper sequence to the device during Reset events. The Reset sources include external

Reset, power-up Reset, and Watchdog Timer (WDT). The IS2083 SoC provides a WDT to Reset the chip. In addition,

it has an integrated Power-on Reset (POR) circuit that resets all circuits to a known Power On state. This action can

also be driven by an external Reset signal, which is used to control the device externally by forcing it into a POR

state. The following figure illustrates the system behavior upon a RST_N event.

Note: The Reset (RST_N) is an active-low signal and can be utilized based on the application needs, otherwise, it

can be left floating.

Figure 6-3. Timing Sequence of Reset Trigger

BAT_IN

SYS_PWR

MFB

VDD_IO

RST_N

BK1

BK2

LDO31

0 ms

200 ms

Note: RST_N pin has an internal pull-up, thus, RST_N signal will transition to high again upon releasing the RST_N

button. This is an expected behavior of RST_N signal.

Figure 6-4. Timing Sequence of Power Drop Protection

RST_N from Reset IC

Power

SYS_PWR

IS2083

Reset

OUT

VDD

GND

MCU Reset

Reset IC

2.93V

2.7V

SYS_PWR

Timing sequence of power drop protection:

• It is recommended to use the battery to provide the power supply at BAT_IN.

• If an external power source or a power adapter is utilized to provide power to BAT_IN, it is recommended to use

a voltage supervisor Integrated Circuit (IC).

• The Reset IC output pin, RST_N, must be open drain type and threshold voltage as 2.93V.

• The RST_N signal must be fully pulled low before SYS_PWR power drop to 2.7V.

BM83

Application Information

Datasheet

DS70005402C-page 42

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