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CD74HC08-Q1

SCLS512B – JULY 2003 – REVISED APRIL 2020

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Copyright © 2003–2020, Texas Instruments Incorporated

Typical Application (continued)

CAUTION

The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings,

is an additional limitation to prevent damage to the device. Do not violate any values

listed in the Absolute Maximum Ratings. These limits are provided to prevent damage

to the device.

9.2.1.2 Input Considerations

Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is

completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used

sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used

for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the

CD74HC08-Q1, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ

resistor value is often used due to these factors.

The CD74HC08-Q1 has standard CMOS inputs, so input signal edge rates cannot be slow. Slow input edge

rates can cause oscillations and damaging shoot-through current. The recommended rates are defined in the

Recommended Operating Conditions.

Refer to the Feature Description for additional information regarding the inputs for this device.

9.2.1.3 Output Considerations

The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will

decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. Similarly, the

ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the

output voltage as specified by the VOL specification in the Electrical Characteristics.

Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.

Refer to Feature Description for additional information regarding the outputs for this device.

9.2.2 Detailed Design Procedure

1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the

device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout.

2. Ensure the capacitive load at the output is

≤ 70 pF. This is not a hard limit, however it will ensure optimal

performance. This can be accomplished by providing short, appropriately sized traces from the CD74HC08-

Q1 to the receiving device.

3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum

output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load

measured in megaohms; much larger than the minimum calculated above.

4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase

can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd

Calculation