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AT42QT1060 [DATASHEET]

9505H–AT42–04/2015

5.

Setups

5.1

Introduction

The device calibrates and processes signals using a number of algorithms specifically designed to provide for high

survivability in the face of adverse environmental challenges. User-defined Setups are employed to alter these

algorithms to suit each application. These Setups are loaded into the device over the I

2C serial interfaces.

Table 5-1.

Internal Register Address Allocation

Address

Use

R/W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

Chip ID

R

Major ID (= 3)

Minor ID (= 1)

1

Version

R

Device version number

2

Minor version

R

Minor version number

3

Reserved

Reserved

4

Detection status

R

Calibrating

Res

Key5

Key4

Key3

Key2

Key1

Key0

5

Input port status

R

Res

Input 6

Input 5

Input 4

Input 3

Input 2

Input 1

Input 0

6–11

Reserved

Reserved

12

Calibrate

R/W

Writing a nonzero value forces a calibration

13

Reset

R/W

Writing a nonzero value forces a reset

14

Drift Option

R/W

Res

Res

Res

Res

Res

Res

Res

DRIFT

15

Positive

Recalibration Delay

R/W

MSB

LSB

16

NTHR key 0

R/W

MSB

LSB

17

NTHR key 1

R/W

MSB

LSB

18

NTHR key 2

R/W

MSB

LSB

19

NTHR key 3

R/W

MSB

LSB

20

NTHR key 4

R/W

MSB

LSB

21

NTHR key 5

R/W

MSB

LSB

22

LP mode

R/W

MSB

LSB

23

I/O mask

R/W

MSB

IO6

IO5

IO4

IO3

IO2

IO1

IO0

24

Key mask

R/W

CAL

Res

Key 5

Key 4

Key 3

Key 2

Key 1

Key 0

25

AKS mask

R/W

Res

Res

Key 5

Key 4

Key 3

Key 2

Key 1

Key 0

26

PWM mask

R/W

Res

IO6

IO5

IO4

IO3

IO2

IO1

IO0

27

Detection mask

R/W

Res

IO6

IO5

IO4

IO3

IO2

IO1

IO0

28

Active level mask

R/W

Res

IO6

IO5

IO4

IO3

IO2

IO1

IO0

29

User output buffer

R/W

Res

IO6

IO5

IO4

IO3

IO2

IO1

IO0

30

DI

R/W

MSB

LSB

31

PWM level

R/W

MSB

LSB