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AT42QT1060 [DATASHEET]

9505H–AT42–04/2015

5.14

Address 24: Key Mask

CAL: this bit controls whether the CAL bit causes a CHG transition.

KEY0 – 5 (Key Mask): these bits control whether a change in the corresponding bit in the detection status register

generates a transition on the CHG line. A 1 allows the status bit to cause a CHG request, a 0 stops the

corresponding bit from causing a CHG request.

Default:

0xBF (all bits create a CHG request)

5.15

Address 25: AKS Mask

KEY0 – 5 (AKS Mask): these bits control which keys are included in the AKS group. A 1 means the corresponding

key is included in the AKS group and may only go into detect when it has the largest signal change of any key in the

group. A 0 means that it is excluded and can go into detect whenever its threshold is passed.

Default:

0x00 (no keys are within the AKS group)

5.16

Address 26: PWM Mask

I/O0 – 6 (PWM Mask): these bits control which I/Os that are configured as outputs, and its user output buffer

activated, will output a PWM signal. A 1 means the output generates a PWM signal, a 0 means the output generates

a logic level. The active level of the output (both logical and PWM) is determined by the Active level mask. See

Section 5.24 on page 24 for I/O register precedence and example usage.

Default:

0x00 (PWM is off on all I/Os)

Table 5-14. Key Mask

Address

b7

b6

b5

b4

b3

b2

b1

b0

24

CAL

Reserved

KEY5

KEY4

KEY3

KEY2

KEY1

KEY0

Table 5-15. AKS Mask

Address

b7

b6

b5

b4

b3

b2

b1

b0

25

Reserved Reserved

KEY5

KEY4

KEY3

KEY2

KEY1

KEY0

Table 5-16. PWM Mask

Address

b7

b6

b5

b4

b3

b2

b1

b0

26

Reserved

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0