FN8862 Rev.1.00

Page 10 of 27

Jul 27, 2017

ISL72027ASEH

2. Specifications

Supply Current, Listen

Mode

ICC(L)

RS = D = VCC, 3V ≤ VCC ≤ 3.6V

Full

-

1

2

mA

Supply Current, Dominant

ICC(DOM) D = RS = 0V, no load, 3V ≤ VCC ≤ 3.6V

Full

-

5

7

mA

Supply Current, Recessive

ICC(REC) D = VCC, RS = 0V, no load,

3V ≤ VCC ≤ 3.6V

Full

-

2.6

5.0

mA

Cold Sparing Bus Current

CANH Leakage Current

IL(CANH)

VCC = 0.2V, CANH = -7V or 12V,

CANL = float, D = VCC, RS = 0V

Full

-25

-4

25

µA

CANL Leakage Current

IL(CANL)

VCC = 0.2V, CANL = -7V or 12V,

CANH = float, D = VCC, RS = 0V

Full

-25

-4

25

µA

VREF Leakage Current

IL(VREF)

VCC = 0.2V, VREF = -7V or 12V, D = VCC

Full

-25

0.01

25

µA

Driver Switching Characteristics

Propagation Delay LOW to

HIGH

tPDLH1

RS = 0V, Figure 14

Full

-

90

160

ns

Propagation Delay LOW to

HIGH

tPDLH2

RS = 10kΩ, Figure 14

Full

-

350

550

ns

Propagation Delay LOW to

HIGH

tPDLH3

RS = 50kΩ, Figure 14

Full

-

475

800

ns

Propagation Delay HIGH to

LOW

tPDHL1

RS = 0V, Figure 14

Full

-

115

180

ns

Propagation Delay HIGH to

LOW

tPDHL2

RS = 10kΩ, Figure 14

Full

-

410

600

ns

Propagation Delay HIGH to

LOW

tPDHL3

RS = 50kΩ, Figure 14

Full

-

550

900

ns

Output Skew

tSKEW1

RS = 0V, (|tPHL - tPLH|), Figure 14

Full

-

20

65

ns

Output Skew

tSKEW2

RS = 10kΩ, (|tPHL - tPLH|), Figure 14

Full

-

60

275

ns

Output Skew

tSKEW3

RS = 50kΩ, (|tPHL - tPLH|), Figure 14

Full

-

75

400

ns

Output Rise Time

tr1

RS = 0V, (fast speed - 1Mbps) Figure 14

Full

15

30

85

ns

Output Fall Time

tf1

Full

10

20

65

ns

Output Rise Time

tr2

RS = 10kΩ, (medium speed - 5000kbps)

Figure 14

Full

125

250

550

ns

Output Fall Time

tf2

Full

100

250

425

ns

Output Rise Time

tr3

RS = 50kΩ, (slow speed - 250kbps)

Figure 14

Full

200

360

800

ns

Output Fall Time

tf3

Full

175

390

600

ns

Total Loop Delay, Driver

Input to Receiver Output,

Recessive to Dominant

t(LOOP1)

RS = 0V, Figure 19

Full

-

140

225

ns

RS = 10kΩ, Figure 19

Full

-

380

600

ns

RS = 50kΩ, Figure 19

Full

-

500

800

ns

Total Loop Delay, Driver

Input to Receiver Output,

Dominant to Recessive

t(LOOP2)

RS = 0V, Figure 19

Full

-

160

285

ns

RS = 10kΩ, Figure 19

Full

-

450

700

ns

RS = 50kΩ, Figure 19

Full

-

575

950

ns

Listen to Valid Dominant

Time

tL-DOM)

Figure 21

Full

-

5

15

µs

Receiver Switching Characteristics

Test Conditions: VCC = 3V to 3.6V; typical values are at TA = +25°C (Note 9); unless otherwise specified (Note 7). Boldface limits apply

across the operating temperature range, -55°C to +125°C and over a total ionizing dose of 75krad(Si) at +25°C with exposure at

a low dose rate of <10mrad(Si)/s. (Continued)

Parameter

Symbol

Test Conditions

Temp

(°C)

Min

(Note 8)

Typ

(Note 9)

Max

(Note 8)

Unit