Application information

L6728

20/32

11.2

Output capacitor(s)

The output capacitors are basic components to define the ripple voltage across the output

and for the fast transient response of the power supply. They depend on the output voltage

ripple requirements, as well as any output voltage deviation requirement during a load

transient.

During steady-state conditions, the output voltage ripple is influenced by both the ESR and

capacitive value of the output capacitors as follow:

Where

∆I

takes in consideration the output capacitor charge and discharge as a consequence of the

inductor current ripple.

During a load variation, the output capacitors supplies the current to the load or absorb the

current stored into the inductor until the converter reacts. In fact, even if the controller

recognizes immediately the load transient and sets the duty cycle at 80% or 0%, the current

slope is limited by the inductor value. The output voltage has a drop that also in this case

depends on the ESR and capactive charge/discharge as follow:

Where

∆V

(

MLCC capacitors have typically low ESR to minimize the ripple but also have low

capacitance that do not minimize the voltage deviation during dynamic load variations. On

the contrary, electrolytic capacitors have big capacitance to minimize voltage deviation

during load transients while they does not show the same ESR values of the MLCC resulting

then in higher ripple voltages. For these reasons, a mix between electrolytic and MLCC

capacitor is suggeted to minimize ripple as well as reducing voltage deviation in dynamic

mode.

11.3

Input capacitors

The input capacitor bank is designed considering mainly the input rms current that depends

input capacitor ESR and, in worst case, are:

∆V

OUT_ESR

∆I

L

ESR

⋅

=

∆V

OUT_C

∆I

L

1

8C

OUT

F

SW

⋅⋅

---------------------------------------

⋅

=

∆V

OUT_ESR

∆I

OUT

ESR

⋅

=

∆V

OUT_C

∆I

OUT

L

∆I

OUT

⋅

2C

OUT

∆V

L

⋅⋅

--------------------------------------

⋅

=

D

MAX

V

IN

V

OUT

–

⋅

I

rms

I

OUT

D1

D

–

()

⋅

⋅

=

PESR

I

⁄

()

2

⋅

=