ACT8846 datasheet(31/63 Pages) QORVO

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ACT8846

Advanced PMU for Multi-core

Application Processors

Data Sheet Rev. 13.0, Nov. 11, 2019 | Subject to change without notice

31 of 63

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Table 3:

ACT8846 and RK31x8 Signal Interface

Note: Typical connections shown, actual connections may vary.

Control Signals

Enable inputs

The ACT8846 features a variety of control inputs, which

are used to enable and disable outputs depending upon

the desired mode of operation. PWRHLD is a logic

inputs, while nPBIN is a unique, multi-function input.

nPBIN Multi-Function Input

The ACT8846 features the nPBIN multi-function pin,

which combines system enable/disable control with a

hardware reset function. Select either of the two pin

functions by asserting this pin, either through a direct

connection to GA as Manual Reset input, or through a

50kΩ resistor to GA for 32ms to enable the IC, or

through a 50kΩ resistor to GA for 10s to disable the IC,

as shown in Figure 2.

Manual Reset Function

The second major function of the nPBIN input is to

provide a manual-reset input for the processor. To man-

ually-reset the processor, drive nPBIN directly to GA

through a low impedance (less than 2.5kΩ). An internal

timer detects the duration of the MR event:

Short Press / Soft-Reset:

If the Manual Reset button is asserted for less than

4s/10s, ACT8846 commences a soft-reset operation

where nRSTO immediately asserts low, then remains

asserted low until the nPBIN input is de-asserted and

the reset time-out period expires. A status bit,

SRSTAT[ ], is set after a soft-reset event. The SRSTAT[ ]

bit is automatically cleared to 0 after read. After Short

Press, set WDSREN[ ] to 1 about 1s after nRSTO

de-assert then clear WDSREN[ ] for properly shutdown

sequence.

Long Press / Power-cycle:

If the Manual Reset button is asserted for more than

4s/10s, ACT8846 commences a power cycle routine

in which case all regulators are turned off and then

turned back on. A status bit, PCSTAT[ ], is set after the

power cycle. The PCSTAT[ ] bit is automatically cleared

to 0 after read.

nPBSTAT Output

nPBSTAT is an open-drain output that reflects the state

of the nPBIN input; nPBSTAT is asserted low whenever

nPBIN is asserted, and is high-Z otherwise. This output

is typically used as an interrupt signal to the processor,

to initiate a software-programmable routine such as op-

erating mode selection or to open a menu. Connect

nPBSTAT to an appropriate supply voltage through a

10kΩ or greater resistor.

Figure 2:

nPBIN Input

nPBIN

ACT8846

Manual

Reset

nPBSTAT

Manual

Reset

Detect

Push-

Button

Detect

To CPU

INL2

VIO

50kΩ

ACT8846

DIRECTION

ROCKCHIP RK31x8

PWREN

GPIO6_B1

SCL

I2C1_SCL

SDA

I2C1_SDA

VSELR2

GPIO0_D7

GPIO1/VSELR3

GPIO0_D6

nRSTO

NPOR

nIRQ

GPIO6_A4

nPBSTAT

GPIO6_A2

PWRHLD

GPIO6_B0



: Only for ACT8846QM468 and ACT8846QM490-T.



: Soft-Reset function is disabled in ACT8846QM460, ACT8846QM468 and ACT8846QM490.



: Only for ACT8846QM460.

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