ACT8846 datasheet(16/63 Pages) QORVO

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ACT8846

Advanced PMU for Multi-core

Application Processors

Data Sheet Rev. 13.0, Nov. 11, 2019 | Subject to change without notice

16 of 63

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BLOCK ADDRESS

BIT

NAME

ACCESS

DESCRIPTION

REG11

0x90

[7:6]

Reserved.

REG11

0x90

[5:0]

VSET

R/W

Output Voltage Selection. See the Output Voltage Programming

section for more information.

REG11

0x91

[7]

R/W

Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit

to 0 to disable the regulator.

REG11

0x91

[6:3]

Reserved.

REG11

0x91

[2]

DIS

R/W

Output Discharge Control. When activated, LDO output is dis-

charged to GA through 1.5kΩ resistor when in shutdown. Set bit to

1 to enable output voltage discharge in shutdown, clear bit to 0 to

disable this function.

REG11

0x91

[1]

nFLTMSK

R/W

Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,

clear bit to 0 to disable fault-interrupts.

REG11

0x91

[0]

Regulator Power-OK Status. Value is 1 when output voltage

exceeds the power-OK threshold, value is 0 otherwise.

REG12

0xA0

[7:6]

Reserved.

REG12

0xA0

[5:0]

VSET

R/W

Output Voltage Selection. See the Output Voltage Programming

section for more information.

REG12

0xA1

[7]

R/W

Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit to

0 to disable the regulator.

REG12

0xA1

[6:3]

Reserved.

REG12

0xA1

[2]

DIS

R/W

Output Discharge Control. When activated, LDO output is dis-

charged to GA through 1.5kΩ resistor when in shutdown. Set bit to

1 to enable output voltage discharge in shutdown, clear bit to 0 to

disable this function.

REG12

0xA1

[1]

nFLTMSK

R/W

Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,

clear bit to 0 to disable fault-interrupts.

REG12

0xA1

[0]

Regulator Power-OK Status. Value is 1 when output voltage

exceeds the power-OK threshold, value is 0 otherwise.

REG13

0xB1

[7]

R/W

Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit to

0 to disable the regulator.

REG13

0xB1

[6:0]

Reserved.

0xC0

nPBAMSK

R/W

nPBIN Assertion Interrupt Control. Set this bit to 1 to generate an in-

terrupt when nPBIN is asserted.

0xC0

nPBDMSK

R/W

nPBIN De-assertion Interrupt Control. Set this bit to 1 to generate an

interrupt when nPBIN is de-asserted.

0xC0

[5:2]

Reserved.

0xC0

WDSREN

R/W

Watchdog Soft-Reset Enable. Set this bit to 1 to enable watchdog

function. When the watchdog timer expires, the PMU commences a

soft-reset routine. This bit is automatically reset to 0 when entering

sleep mode.

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