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MAS9090BS датащи(PDF) 20 Page - Micronas |
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MAS9090BS датащи(HTML) 20 Page - Micronas |
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20 / 30 page ![]() DA9090B.001 January 14, 1998 20 FUNCTIONAL DESCRIPTION Control register CR0 7 6 5 4 3 2 1 0 Function F1 F0 CM MA IA FF B7 DL 0 0 1 1 0 1 0 1 MCLK = 512 kHz * MCLK = 1536 kHz MCLK = 2048 kHz Not implemented 0 0 0 1 1 0 1 0 1 Linear code * 2’s complement * sign and magnitude 2’s complement 1’s complement 1 0 0 1 1 0 1 0 1 Companded code µ-Law: CCITT D3-D4 µ-Law: bare coding A-Law: including even bit inversions A-Law: bare coding 0 1 B1 and B2 consecutive (1)* B1 and B2 separated (1) 0 1 8-bit time slot (1)* 7-bit time slot (1) 0 1 Normal operation (default) * Digital loop back (TX and RX muted) Control register CR1 7 6 5 4 3 2 1 0 Function TM1 TM0 DO MR MX EN TS SV 0 1 1 X 0 1 Delayed data timing * Non-delayed normal data timing Non-delayed reverse data timing 0 1 LO latch set to 1 * LO latch set to 0 0 1 RX connected to RX path * CR2 connected to RX path (1) 0 1 TX path connected to TX * CR3 connected to TX (1) 0 1 Voice data transfer disable * Voice data transfer enable 0 1 B1 channel selected (1)* B2 channel selected (1) 0 1 2.7-3.6V power supply * 5.0V power supply (1) significant in companded mode only * state at power on initialization |
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