DA9090B.001

January 14, 1998

19

FUNCTIONAL DESCRIPTION

x Registers

Register Map

Register

Address Byte

I/O

Data Byte

76

54

3

2

1

0

76

5

4

3

2

10

Power

P

X

X

X

X

X

0

X

CR0

P

0

0

0

0

0

1

X

Write

F1

F0

CM

MA

IA

FF

B7

DL

P

0

0

0

0

1

1

X

Read

CR1

P

0

0

0

1

0

1

X

Write

DM1

DM0

DO

MR

MX

EN

TS

SV

P

0

0

0

1

1

1

X

Read

CR2

P

0

0

1

0

0

1

X

Write

Input data [0:7]

P

0

0

1

0

1

1

X

Read

CR3

P

0

0

1

1

0

1

X

Write

Output data [0:7]

P

0

0

1

1

1

1

X

Read

CR4

P

0

1

0

0

0

1

X

Write

VS

TE

SI

OE1

OE2

RTE

HPR

SE

P

0

1

0

0

1

1

X

Read

CR5

P

0

1

0

1

0

1

X

Write

TX gain [4:7]

Side tone gain [0:3]

P

0

1

0

1

1

1

X

Read

CR6

P

0

1

1

0

0

1

X

Write

SP1 gain [4:7]

SP2 gain [0:3]

P

0

1

1

0

1

1

X

Read

CR7

P

0

1

1

1

0

1

X

Write

Tone gain [4:7]

F1

F2

SN

DE

P

0

1

1

1

1

1

X

Read

CR8

P

1

0

0

0

0

1

X

Write

Binary word used for calculating f1

P

1

0

0

0

1

1

X

Read

CR9

P

1

0

0

1

0

1

X

Write

Binary word used for calculating f2

P

1

0

0

1

1

1

X

Read

CR10

P

1

0

1

0

0

1

X

Write

POR

SCA

HPT

EXT

LI

LO

DFT

HFT

P

1

0

1

0

1

1

X

Read

CR11

P

1

0

1

1

0

1

X

Write

BE

BI

Duty cycle for BZ (0:5)

P

1

0

1

1

1

1

X

Read

CR14

X

X

X

X

X

X

X

X

For testing purposes only

Address byte bits:

•

Bit 0 reserved for future extensions

•

Bit 1 indicates the presence of a second byte. If cleared indicates single byte power up/down command

•

Bit 2 is write/read select bit

•

Bits 6 to 3 contain the address of register

•

Registers CR12, CR13, CR15 are not accessible

•

MSB bit (bit 7) of the address and data byte is always clocked first into or out from CI and CO pins

•

Bit 7 ‘P’ controls the power up/down state of the chip. P = 1 means power down

Data bits:

•

All registers are cleared during power on reset or by writing to bit POR of CR10

•

Default value for all bits is zero.

Notice the difference between power down and POR. Registers can be written in both power down/up states and

they retain their values in power down. Both data and control registers are cleared when POR bit (in CR10) is

written high or during power on reset (i.e. Vcc transition from 0 volts to 3-5 volts).