Data Sheet

AD8488

Rev. A | Page 7 of 20

KEY

AVDD

AGND

DGND

DVDD

I/O

DIG I/O

NC

A1 BALL PAD CORNER

NOTE: E12 AND M12 ARE NC ON THE BGA BUT

MUST BE CONNECTED TO GROUND ON THE PCB

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

BOTTOM VIEW

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

Figure 3. 255-Ball CSP_BGA Ball Configuration (Bottom View)

Table 5. Pin Function Descriptions

Mnemonic

Pin No.

I/O

Description

AGND

See Table 6 and Table 7

O

Analog Power Ground (0 V).

AVDD

F6, F7, F8, F9, F10, G6, G11, H6, H11, H12, J6,

J11, K6, K11, L6, L8, L9, L10, L11

I

Analog Supply Voltage (5 V).

CLK

D15

I

Clock for Mux Operation.

CK_ENa

E14

I

Clock Gate for Channel 0 to Channel 63.

CK_ENb

F14

I

Clock Gate for Channel 64 to Channel 127.

CS_A

N14

I

Logic Level to Enable Channel 0 to Channel 63.

CS_B

M15

I

Logic Level to Enable Channel 64 to Channel 127.

CF1SEL0,

CF1SEL1

B15, C15

I

Binary Coded Logic Pins to Select One of Four Values of Integrator

Capacitor CF1 (see Table 9).

DGND

F16, G15, G16, H15, H16, J15, J16, K15, K16, L16

O

Digital Ground (0 V).

DVDD

B16, C16, D16, E16, F15, L15, M16, N16, P16, R16

I

Power Supply for Digital Circuit (5 V).

FSEL0, FSEL1

R14, T14

I

Filter Time Constant Select (see Table 10).

GNSEL0 to

GNSEL3

A14, B14, C14, D14

I

Gain Select for the Gain Amp. Select one of four hold capacitors. The

four values are arranged in one of ten parallel options to establish ten

gain values (see Table 11).

GRST

H14

I

Gain Amp Reset. Closes the switch across Integrator Capacitor CF2

setting the output of the gain amplifier to zero.

HOLD

T16

I

Gain Amp Hold. Connect the hold capacitor to the signal chain.