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PCM1774 датащи(PDF) 20 Page - Texas Instruments

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номер детали PCM1774
подробное описание детали  16-Bit, Low-Power Stereo Audio DAC With Analog Mixing, Line and Headphone Outputs
PDF  49 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
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PCM1774 датащи(HTML) 20 Page - Texas Instruments

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Three-Wire Interface (SPI) Timing Requirements
tw(MCH)
50%ofVIO
MS
t(MLS)
LSB
50%ofVIO
50%ofVIO
tw(MCL)
tw(MHH)
t(MLH)
t(MCY)
t(MDH)
t(MDS)
MC
MD
T0013-08
TWO-WIRE INTERFACE [I
2C, MODE (PIN 28) = HIGH]
SLAVE ADDRESS
PCM1774
SLAS551 – JULY 2007
Figure 19 shows a detailed timing diagram for the serial control interface. These timing parameters are critical
for proper control port operation.
PARAMETERS
MIN
TYP
MAX
UNIT
t(MCY)
MC pulse cycle time
500(1)
ns
tw(MCL)
MC low level time
50
ns
tw(MCH)
MC high level time
50
ns
tw(MHH)
MS high level time
See(1)
ns
t(MLS)
MS falling edge to MC rising edge
50
ns
t(MLH)
MS hold time
20
ns
t(MDH)
MD hold time
15
ns
t(MDS)
MD setup time
20
ns
(1)
3/(128 fS) s (min), where fS is sampling rate.
Figure 19. SPI Interface Timing
The PCM1774 supports the I2C serial bus and the data transmission protocol for the I2C standard as a slave
device. This protocol is explained in I2C specification 2.0.
In I2C mode, the control terminals are changed as follows.
TERMINAL NAME
PROPERTY
DESCRIPTION
MS/ADR
Input
I2C address
MD/SDA
Input/output
I2C data
MC/SCL
Input
I2C clock
MSB
LSB
1
0
0
0
1
1
ADR
R/W
The PCM1774 has its own 7-bit slave address. The first six bits (MSBs) of the slave address are factory preset
to 100011. The last bit of the address byte is the device select bit, which can be user-defined by the ADR
terminal. A maximum of two PCM1774 can be connected on the same bus at one time. The PCM1774 responds
when it receives its own slave address.
20
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