TMP86FS49AIUG datasheet(186/296 Pages) TOSHIBA

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Page 170

14. Synchronous Serial Interface (SIO1)

14.3 Function

TMP86FS49AIUG

Figure 14-11 Example of External Clock and MSB Receive Mode

(4)

Receive error processing

Receive errors occur on the following situation. To protect SIO1RDB and the shift register con-

tents, the received data is ignored while the SIO1SR<RXERR> is “1”.

• Shift operation is finished before reading out received data from SIO1RDB at

SIO1SR<RXF> is “1” in an external clock operation.

If receive error occurs, set the SIO1CR<SIOS> to “0” for reading the data that received

immediately before error occurence. And read the data from SIO1RDB. Data in shift register

(at errors occur) can be read by reading the SIO1RDB again.

When SIO1SR<RXERR> is cleared to “0” after reading the received data, SIO1SR<RXF> is

cleared to “0”.

After clearing SIO1CR<SIOS> to “0”, when 8-bit serial clock is input to SCK1 pin, receive

operation is stopped. To restart the receive operation, confirm that SIO1SR<SIOF> is

cleared to “0”.

If the receive error occurs, set the SIO1CR<SIOINH> to “1” for stopping the receive opera-

tion immediately. In this case, SIO1CR<SIOS>, SIO1SR register, SIO1RDB register and

SIO1TDB register are initialized.

Reading received

data C

Reading received

data B

Reading received

data A

A7 A6

A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0

Start shift

operation

Start shift

operation

Start shift

operation

Clearing SIOS

Reading received data

SIO1CR<SIOS>

SIO1SR<SIOF>

SIO1SR<SEF>

SCK1

SI1 pin

SIO1SR<RXF>

INTSIO1

interrupt

request

SIO1RDB

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