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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMP86FS49AIUG датащи(PDF) 185 Page - Toshiba Semiconductor |
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TMP86FS49AIUG датащи(HTML) 185 Page - Toshiba Semiconductor |
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185 / 296 page  Page 169 TMP86FS49AIUG If received data is not read out from SIO1RDB receive error occurs immediately after shift opera- tion is finished. Then INTSIO1 interrupt request is generated after SIO1SR<RXERR> is set to “1”. (3) Stopping the receive operation There are two ways for stopping the receive operation. • The way of clearing SIO1CR<SIOS>. When SIO1CR<SIOS> is cleared to “0”, receive operation is stopped after all of the data is finished to receive. When receive operation is finished, SIO1SR<SIOF> is cleared to “0”. In external clock operation, SIO1CR<SIOS> must be cleared to “0” before SIO1SR<SEF> is set to “1” by starting the next shift operation. • The way of setting SIO1CR<SIOINH>. Receive operation is stopped immediately after SIO1CR<SIOINH> is set to “1”. In this case, SIO1CR<SIOS>, SIO1SR register, SIO1RDB register and SIO1TDB register are initialized. Figure 14-10 Example of Internal Clock and MSB Receive Mode A6 A5 A4 A3 A2 A1 A0 A7 B7 B6 B5 B4 B3 B2 B1 C7 B0 C6 C5 C4 C3 C2 C1 C0 B A C Automatic wait Start shift operation Start shift operation Start shift operation Reading received data A Reading received data B Clearing SIOS Reading received data C SIO1CR<SIOS> SIO1SR<SIOF> SIO1SR<SEF> SCK1 pin SI1 pin SIO1SR<RXF> INTSIO1 interrupt request SIO1RDB |
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