TMP88CU74F datasheet(58/132 Pages) TOSHIBA

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TMP88CU74

2003-02-17

88CU74-58

Table 2.4.1 Watchdog Timer Detection Time (Example: fc

= 12.5 MHz, fs = 32.8 kHz)

Watchdog Timer Detection Time [s]

NORMAL1/2 Mode

DV7CK

= 0

DV7CK

= 1

WDTT

DV1CK

= 0

DV1CK

= 1

DV1CK

= 0

DV1CK

= 1

SLOW Mode

2.684 s

671.089 ms

167.772 ms

41.943 ms

5.369 s

1.342 s

335.544 ms

83.886 ms

250

62.5 ms

250

62.5 ms

250

62.5 ms

2.4.3

Watchdog Timer Interrupt (INTWDT)

This is a pseudo non-maskable interrupt which can be accepted regardless of the

contents of the EIR. If a watchdog timer interrupt or a software interrupt is already

accepted, however, the new watchdog timer interrupt waits until the previous interrupt

processing is completed (the end of the [RETN] instruction execution).

The stack pointer (SP) should be initialized before using the watchdog timer output as an

interrupt source with WDTOUT.

Example: Watchdog timer interrupt setting up

SP, 0023FH

;

Sets the stack pointer

(WDTCR1), 00001000B

;

WDTOUT

← 0

2.4.4

Watchdog Timer Reset

If the watchdog timer output becomes active, a reset is generated, which drives the

RESET

pin (sink open drain input/output with pull-up) low to reset the internal hardware

and external circuits. The reset output time is about 8/fc to 24/fc [s] (0.64 to 1.92

μs at fc =

12.5 MHz, fcgck = fc).

Note:

The high-frequency clock oscillator also turns on when a watchdog timer reset is

generated in SLOW mode. The reset output time is 8/fc to 24/fc [s]. Therefore, the reset

time may include a certain amount of error if there is any fluctuation of the oscillation

frequency at starting the high-frequency clock oscillation. Thus, the reset time must be

considered an approximated value.

Figure 2.4.3 Watchdog Timer Interrupt/Reset

Clock

Binary counter

Overflow

INTWDT interrupt

WDT reset output

(WDTT

= 11B)

(“L” output)

(High-Z)

Writes 4EH to WDTCR2

17/fc

19/fc [s]

2007-10-19

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