All trademarks mentioned in this document

http://www.DigitalCoreDesign.com

are trademarks of their respective owners.

http://www.dcd.pl

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

flags are set automatically when the corre-

sponding event occur and cleared by software

sequence.

Slave Select Control Register

configures

which slave select output should be driven

while SPI master transfer. Contents of SSCR

register is automatically assigned on SS7O-

SS0O pins when DSPI master transmission

starts.

SPI Clock Logic

- Software can select any of

four combinations of serial clock (SCK) phase

and polarity using two bits in the SPI control

register (SPCR). The clock polarity is specified

by the CPOL control bit, which selects an ac-

tive high or active low clock and has no sig-

nificant effect on the transfer format. The clock

phase (CPHA) control bit selects one of two

fundamentally different transfer formats. The

clock phase and polarity should be identical

for the master SPI device and the communi-

cating slave device. In some cases, the phase

and polarity are changed between transfers to

allow a master device to communicate with

peripheral slaves having different require-

ments. The flexibility of the SPI system on the

DSPI allows direct interface to almost any

existing synchronous serial peripheral.

SPI Controller

manages the Master/Slave

operation and controls the transmission. The

SPI Controller manages the transmission

speed and format (Phase and polarity). Con-

troller is also responsible for generating of

interrupt request and detection of transmission

errors.

PERFORMANCE

The following table gives a survey about

the Core performance in the ALTERA® de-

vices after Place & Route (all key features

have been included):

Device

Speed

grade

Logic Cells

CYCLONE

-6

181

303 MHz

CYCLONE2

-6

172

310 MHz

STRATIX

-5

181

320 MHz

STRATIX2

-3

151

387 MHz

STRATIXGX

-5

181

307 MHz

APEX2A

-7

196

244 MHz

APEX20KC

-7

196

211 MHz

APEX20KE

-1

196

169 MHz

APEX20K

-1

196

135 MHz

ACEX1K

-1

205

156 MHz

FLEX10KE

-1

205

156 MHz

MAX2

-3

181

209 MHz

MAX3K

-5

119

96 MHz

MAX7K

-5

119

96 MHz

Core performance in ALTERA® devices