All trademarks mentioned in this document

http://www.DigitalCoreDesign.com

are trademarks of their respective owners.

http://www.dcd.pl

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

SYMBO L

datai(7:0)

addr(1:0)

scki

mi

si

clk

rst

datao(7:0)

cs

rd

we

ss7o

ss6o

ss5o

ss4o

ss3o

ss2o

ss1o

ss0o

scko

scken

mo

so

soen

irq

ss

PINS DESCRIPTION

PIN

TYPE

DESCRIPTION

clk

input

Global clock

rst

input

Global reset

datai(7:0)

input

Data bus input

addr(1:0)

input

Processor address lines

cs

input

Chip select

rd

input

Processor read strobe

we

input

Processor write strobe

scki

input

SPI clock input

mi

input

Master serial data input

si

input

Slave serial data input

ss

input

Slave select

datao(7:0)

output

Data bus output

irq

output

Interrupt request

scko

output

SPI clock output

sckz

output

SPI clock output enable

mo

output

Master serial data output

so

output

Slave serial data output

ss7o-ss0o

output

Slave select outputs

BLOCK DIAGRAM

Shift register and Read Data Buffer

– it is a

central element in the SPI system. The sys-

tem is single buffered in the transmit direction

and double buffered in the receive direction.

This fact means new data for transmission

cannot be written to the shifter until the previ-

ous transaction is complete; however, re-

ceived data is transferred into a parallel read

data buffer so the shifter is free to accept a

second serial character. As long as the first

character is read out of the read data buffer

before the next serial character is ready to be

transferred, no overrun condition will occur.

When an SPI transfer occurs, an 8-bit char-

acter is shifted out on data pin while a differ-

ent 8-bit character is simultaneously shifted in

a second data pin. Another way to view this

transfer is that an 8-bit shift register in the

master and another 8-bit shift register in the

slave are connected as a circular 16-bit shift

register. When a transfer occurs, this distrib-

uted shift register is shifted eight bit positions;

thus, the characters in the master and slave

are effectively exchanged.

8-Bit Shift Register

Read Data Buffer

MSB

LSB

SPI Clock

Logic

Divider

÷4 - ÷512

SPI Control Reg.

SPI Status Reg.

clk

SPR

CPHA

CPOL

SPI

Controller

mo

so

mi

si

scko

scki

scken

datao

ss

SS Control Reg.

ss7o

ss6o

ss5o

ss4o

ss3o

ss2o

ss1o

ss0o

datai

addr

cs

we

rd

soen

Control Register

may be read or written at

any time, is used to configure the DSPI Sys-

tem. This register controls the mode of trans-

mission (Master, Slave), polarity and phase of

SPI Clock and transmission speed.

Status Register

(SPSR) is read only register

contains flags indicating the completion of

transfer or occurrence of system errors. All