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Bus Controller

– Program Memory, Data

Memory & SFR’s (Special Function Register)

interface controls access into the program and

data memories and special registers. It con-

tains Program Counter (PC), Stack Pointer

(SP) register, and related logic.

portao(7:0)

portdo(7:0)

portco(7:0)

portbo(7:0)

datai(7:0)

clk

rst

datao(7:0)

cap1

cap2

BUS

Controller

I/O

Ports

Opcode

Decoder

Interrupt

Controller

Timer

with

Compare /

Capture

Unit

SCI Unit

irq

cmp1

cmp2

txd

rxd

ramoe

ramwe

addr(23:0)

halt

portai(7:0)

portdi(7:0)

portci(7:0)

portbi(7:0)

ddra(7:0)

ddrd(7:0)

ddrc(7:0)

ddrb(7:0)

Watchdog

Timer

ALU

prgdata(7:0)

prgaddr(15:0)

prgoe

ufroe

ufrwe

ufraddr(5:0)

ready

Control

Unit

DoCD

TM

Debugger

docdclk

docddatai

docddatao

prgwe

clkdocd

Interrupt Controller

- DF6805 extended IC

has implemented 7-level interrupt priority con-

trol. The interrupt requests may come from

external pin (IRQ) as well as from particular

peripherals. The DF6805 peripheral systems

generate maskable interrupts, which are rec-

ognized only if the global interrupt mask bit (I)

in the CCR is cleared. Maskable interrupts are

prioritized according to default arrangement

established during reset. When interrupt con-

dition occurs, an interrupt status flag is set to

indicate the condition.

I/O Ports

- All ports are 8-bit general-purpose

bi-directional

I/O

system.

The

PORTA,

PORTB, PORTC, PORTD data registers have

their corresponding data direction registers

DDRA, DDRB, DDRC, DDRD to control ports

data flow. It assures that all DF6805’s ports

have full I/O selectable registers. Writes to

any ports pins cause data to be stored in the

data registers. If any port pins are configured

as output then data registers are driven out of

those pins. Reads from port pins configured

as input causes that input pin is read. If port

pins is configured as output, during read data

register is read. Writes to any ports pins not

configured as outputs do not cause data to be

driven out of those pins, but the data is stored

in the output registers. Thus, if the pins later

become outputs, the last data written to port

will be driven out the port pins.

Timer & Compare

- The programmable timer

is based on free-running 16-bit counter with a

fixed divide by four prescaler. plus input cap-

ture/output compare circuitry. The timer can

be used for many purposes including measur-

ing pulse length of two input signals and gen-

erating two output signals. The timer has 16-

bit architecture, hence each specific functional

segment is represented by two 8-bit registers.

These registers contains the high and low

byte of that functional block. Accessing the

low byte of a specific timer function allows full

control of that function, however, an access of

the high byte inhibits that specific timer func-

tion until the byte is also accessed.

Each of the input-capture channel has its own

16-bit time capture latch (input-capture regis-

ter) and each of the output-compare channel

has its own 16-bit compare register. Additional

control bits permit software to control the

edge(s) that trigger each input-capture func-

tion and the automatic actions that result from

output-compare functions. Although hardwired

logic is included to automate many timer ac-

tivities, this timer architecture is essentially a

software-oriented system. This structure is

easily adaptable to a very wide range of appli-

cations although it is not as efficient as dedi-

cated hardware for some specific timing appli-

cations.

Watchdog Timer -

The Watchdog Timer con-

trol logic. The Watchdog Timer can be en-

abled by software by writing ‘1’ to the WDOG

bit in MISC register ($000C). Once enabled

the WDT Timer cannot be disabled by soft-

ware. In addition the WDOG bit acts as a re-

set mechanism for the WDT Timer. Writing

logic one ‘1’ to the WDOG bit clears Watch-

dog counter and inhibits Watchdog timeout